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Observer
Observer
513 Views
Registered: ‎01-24-2019

Synthesized schematic does not match code

Hello,
We are having a size fitting issue with a custom PWM timer. The code seems simple and we expect to consume lower than the tool is currently requesting. We attempted to debug the design to better understand what causing the size to blow up. To simplify debugging, we took the simplest sub module we have and tried to follow it through the different implementation stages. However, we can’t seem to understand what the tool is doing based on the synthesized schematic view. Our understanding is that the synthesized output will not include any routing logic. This making us expect that the synthesized schematic view should have a close resemblance to the code which is currently not the case.
The source code files for the sub module in question are attached. The module consists of 8 identical auto-generated output capture units. Each unit is basically comparing two 32bit values and generating an event when there is a match. The RTL schematic shows proper block diagram (attached) but when we look at the synthesized schematic (pics attached), it doesn’t show the proper input and output signals and every identical auto generated output capture has a completely different I/O and internal implementation. I would not assume this output from the tool and it is making it impossible to debug the design. Please help us understand why the tool producing this output.
Thanks!
Mustafa

RTL_OC_Gen0.png
Synthesized_OC_Gen0.png
Synthesized_OC_Gen1.png
Synthesized_OC_Gen5.png
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6 Replies
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Scholar
Scholar
488 Views
Registered: ‎08-01-2012

Dont really understand the problem.

Does it work or not? Is the problem that the schematic is not what you expected? What exactly are you trying to debug?

Synthesis will do it's job of reducing logic by doing things like merging duplicate cells and registers. Path names often get renamed too (to something usually unhelpful). You can keep nets with the "DONT_TOUCH" attribute.

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Observer
Observer
480 Views
Registered: ‎01-24-2019

The problem is the schematic is not what we expect based on the code. 

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Xilinx Employee
Xilinx Employee
454 Views
Registered: ‎05-14-2008

The synthesize result you observed is reasonable.

The -flatten_hierarchy option of Synthesis is default to "rebuilt", which means Synthesis will first flatten the RTL hierarchy to perform cross-boundary optimization such as trimming, sharing, retiming and etc. And then at the end of Synthesis, it will try to rebuild the hierarchy as close as to the original RTL. 

During the cross-boundary optimization, logics could be moved across hierarchies. So you may see one module has less logics than expected and the other one has more. And the pins on hierarchy boundary may not be able to be restored due to those optimizations. 

For debug purpose, you can set -flatten_hierarchy to none so that Synthesis will preserve all hierarchies and there will be no cross-hierarchy optimizations.

Hope this helps.

-vivian

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Observer
Observer
386 Views
Registered: ‎01-24-2019

Thanks Vivian. You are correct the flatten_hierarchy option was set to debug. However, changing it to "none" and rerun synthesis still did not make any noticable changes on the schematic.

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Xilinx Employee
Xilinx Employee
362 Views
Registered: ‎05-14-2008

@mustafa.homsi 

Can you post the code in OutputCaptures module?

Are you using generate statement?

You can also try applying "keep_hierarchy" constraint to the OutputCapture module.

(*keep_hierarchy="true"*) module OutputCapture

-vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Observer
Observer
339 Views
Registered: ‎01-24-2019

I am using a generate statment and outputCaptures code was attached to the first post. Here it is again for reference.

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