11-14-2013 07:36 AM
I would like to ask: Can Vivado synthesize latch-based designs?
I´m in a company that does processor design for ASICs. We are using Xilinx FPGAs for prototyping but aren´t happy with the workflow. The main problem is, that until now Xilinx ISE was not able to synthesize our processor (latch-based design, non-overlapping clocks), so we had to use a Synopsys tool for that. Then import the Synopsys output into ISE and proceed to get it onto the FPGA. This is possible, but has quite some downsides: often the constraints written out by the Synopsys tool weren´t recognized in ISE, so we had to manually adjust them. If there are problems it´s always hard to decide which tool is having a problem and even harder to get support, because whoever you ask, it´s always the tool of the other company which is to blame. And even if you get it to work a some point, one update of either tool might just cause new problems.
So since Vivado is all new and better than ISE, maybe it would be able to do the job alone?
Thanks for your input.
11-14-2013 09:47 AM
11-16-2013 02:03 AM
11-26-2013 06:19 AM
Thanks for your feedback. Sorry for the late reply, it took some time to get the design ported to Vivado.
I think you´re right. The problem did occur in the timing. But it was a result of the synthesis. We have this non-overlapping clock which is synthesized by one clock and another one that is derived from the first one. The second one is generated by routing the first one as close as possible to the connected module(s) and latches, then change from the clock tree to a logic cell (inverter, clock-gating) and then continue. This brings logic elements into the clock path which induce delay and then skew. And that brings a lot timing violations.
Synopsys Synplify understands this type of clock and then does some sort of clock conversion into a FPGA-friendly clock. And that makes it possible to run it on a FPGA.
Yes, I know that Xilinx doesn´t support designs with latches. But thanks for pointing that out - I thought this might have changed in Vivado.
So, I imported the design into Vivado. At first it was looking the same as in ISE. I then discovered that the new clock module (MMCM) offers a lot more possibilities than before. With this it was possible to generate two non-overlapping clocks very close to the ones we have in an ASIC. After some tweaking I got rid of almost all timing violations and even got a simulation running. I can´t say it´s working yet - I still have to add more constraints and do a functional check, but it looks better than in ISE. Am I on the right way?
12-17-2013 07:54 AM