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Anonymous
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Synthesizing latch-based designs in Vivado

Hello,

 

I would like to ask: Can Vivado synthesize latch-based designs?

 

I´m in a company that does processor design for ASICs. We are using Xilinx FPGAs for prototyping but aren´t happy with the workflow. The main problem is, that until now Xilinx ISE was not able to synthesize our processor (latch-based design, non-overlapping clocks), so we had to use a Synopsys tool for that. Then import the Synopsys output into ISE and proceed to get it onto the FPGA. This is possible, but has quite some downsides: often the constraints written out by the Synopsys tool weren´t recognized in ISE, so we had to manually adjust them. If there are problems it´s always hard to decide which tool is having a problem and even harder to get support, because whoever you ask, it´s always the tool of the other company which is to blame. And even if you get it to work a some point, one update of either tool might just cause new problems.

 

So since Vivado is all new and better than ISE, maybe it would be able to do the job alone?

Thanks for your input.

 

Sandro  

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Teacher
Teacher
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Registered: ‎03-31-2012

What were the synthesis problems you had with XST in synthesizing latch based design? I think the problem would be in not synthesis but checking timing. I would try Vivado with synthesis again and see what it does.
With Vivado you should have better luck with timing because it understands a version of SDC type timing constraints so reading in Synopsys generated constraints into Vivado should be easier.
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Moderator
Moderator
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Registered: ‎04-17-2011

Xilinx always discourages designs with Latches but it would be seen as Warnings in Synthesis tools. Synthesis would pass and you would see Latch Elements LD/LDCE etc in the generated netlist. But as muzaffer correctly pointed out, you would face difficulties in closing timing. Give a run and post your feedback.
Regards,
Debraj
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Anonymous
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Thanks for your feedback. Sorry for the late reply, it took some time to get the design ported to Vivado.

 

@muzaffer

I think you´re right. The problem did occur in the timing. But it was a result of the synthesis. We have this non-overlapping clock which is synthesized by one clock and another one that is derived from the first one. The second one is generated by routing the first one as close as possible to the connected module(s) and latches, then change from the clock tree to a logic cell (inverter, clock-gating) and then continue. This brings logic elements into the clock path which induce delay and then skew. And that brings a lot timing violations.

 

Synopsys Synplify understands this type of clock and then does some sort of clock conversion into a FPGA-friendly clock. And that makes it possible to run it on a FPGA.

 

@debrajr

Yes, I know that Xilinx doesn´t support designs with latches. But thanks for pointing that out - I thought this might have changed in Vivado.

 

So, I imported the design into Vivado. At first it was looking the same as in ISE. I then discovered that the new clock module (MMCM) offers a lot more possibilities than before. With this it was possible to generate two non-overlapping clocks very close to the ones we have in an ASIC. After some tweaking I got rid of almost all timing violations and even got a simulation running. I can´t say it´s working yet - I still have to add more constraints and do a functional check, but it looks better than in ISE. Am I on the right way?

 

Regards.

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Anonymous
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Short Update:

I simulated the design and was able to confirm that it´s working. So the synthesis tool has definitely improved over the one in ISE.  

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Moderator
Moderator
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Registered: ‎06-05-2013

Thanks for your feedback.

We appreciate your efforts due to which we are able to improve the quality of our tool.

Thanks
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