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Adventurer
Adventurer
299 Views
Registered: ‎01-19-2018

Synthesizing out async reset

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I have a design where all sub-modules receive active high async reset and sync reset. When any of the signals are are asserted, then the lowest level registers are reset. Please for the time being, ignore the need to keep both in my design RTL.

In reality I only use the sync reset. So in the top module I am driving the top-level async_rst signal like : global_arst <= '0';

It is connected but always connected to '0', i.e. de-asserted.

During design synthesis stage, will Vivado synthesize out this global_arst as because I am driving this to always '0'? Meaning the lowest level registers will never see this global_arst?

 

 

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Xilinx Employee
Xilinx Employee
251 Views
Registered: ‎07-14-2011

Re: Synthesizing out async reset

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Hi,

Without a code snippet, I cannot say for sure what could happen.  But it is possible there is flow issue preventing you from getting desired result.  So this is to explain what the flow looks like.

Elaboration of the HDL code happens within a module before constant can be propagated into design hierarchies.  That means the tool cannot see the async reset as a constant during elaboration and it's viewed as an active signal.  With both active signals for async reset and sync reset, the tool will pick async reset when inferring the register type (Xilinx register can have either async reset or sync reset, but not both).  The sync reset will likely become logic gates feeding the D input of the register. 

Later in the flow, constant propagation happens, and the async reset to the register will be connected to ground.  The tool also has code to "re-discover" sync reset, but it may not for all the cases.

 

7 Replies
285 Views
Registered: ‎06-21-2017

Re: Synthesizing out async reset

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Ignoring the two resets is difficult, but I will force myself.

Vivado should optimize out the constant, non-asserted reset.  One way to prevent this is to connect the reset to an unused pin and place a pull-up or pull-down resistor in the constraints file to keep the signal at the non-asserted state.

Adventurer
Adventurer
266 Views
Registered: ‎01-19-2018

Re: Synthesizing out async reset

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@bruce_karaffa,

I want the synth to optimize out that never toggling async reset. I had a doubt and so was asking this.

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Xilinx Employee
Xilinx Employee
252 Views
Registered: ‎07-14-2011

Re: Synthesizing out async reset

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Hi,

Without a code snippet, I cannot say for sure what could happen.  But it is possible there is flow issue preventing you from getting desired result.  So this is to explain what the flow looks like.

Elaboration of the HDL code happens within a module before constant can be propagated into design hierarchies.  That means the tool cannot see the async reset as a constant during elaboration and it's viewed as an active signal.  With both active signals for async reset and sync reset, the tool will pick async reset when inferring the register type (Xilinx register can have either async reset or sync reset, but not both).  The sync reset will likely become logic gates feeding the D input of the register. 

Later in the flow, constant propagation happens, and the async reset to the register will be connected to ground.  The tool also has code to "re-discover" sync reset, but it may not for all the cases.

 

Adventurer
Adventurer
202 Views
Registered: ‎01-19-2018

Re: Synthesizing out async reset

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Thanks for the nice explanation @bingt .

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Registered: ‎01-08-2012

Re: Synthesizing out async reset

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@bingt wrote:

Later in the flow, constant propagation happens, and the async reset to the register will be connected to ground.  The tool also has code to "re-discover" sync reset, but it may not for all the cases.


My experience with multiple versions of Vivado is that it typically won't "re-discover" the sync reset.  In some cases this means that the LUT count will be higher than it needs to be, and the only fix is to rewrite the source code without the reset.  I've seen extreme cases where removing async resets meant the difference between fitting and not fitting into a device.

This is unfortunate, because many historical coding guides (including Xilinx's) said to use async resets.

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Adventurer
Adventurer
130 Views
Registered: ‎01-19-2018

Re: Synthesizing out async reset

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@allanherriman,

My experience with multiple versions of Vivado is that it typically won't "re-discover" the sync reset. In some cases this means that the LUT count will be higher than it needs to be, and the only fix is to rewrite the source code without the reset. I've seen extreme cases where removing async resets meant the difference between fitting and not fitting into a device.

Yes, when I comment out the async reset signals I only see a 7% decrease in LUT count(Artix-7). Since the async_reset signal is tied to '0' at the top_level and it is not at all toggling, I expect xilinx synthesis to optimize it out. Most probably that is happening.

This is unfortunate, because many historical coding guides (including Xilinx's) said to use async resets.

Possibly true, but here I did not follow any xilinx template. It was kept in the RTL for an entirely different reason. I don't want to go into the discussion whether it is needed or not.

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Registered: ‎01-22-2015

Re: Synthesizing out async reset

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@gin_xil 

You may find the recent discussion <here> about async resets to be helpful. 

-the conclusion being that use of synchronous resets (instead of asynchronous resets) is now strongly recommend by Xilinx.

Mark

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