11-03-2020 09:38 AM
I integrated a verified design into a larger system. Both system so far were easy (fast) to synthesize. Now after the integration the projects takes forever, meaning I let it run over night and it did not finish (>6h). So from minutes to several hours seem impossible.
In vivado I seem to have no way of tellig what happens during synthesis. It is very annoying that only one CPU is used, but even this would only make my design run 20 times faster and is not the factor I am looking for.
So my question is on general: How do I approach this issue in vivado. How to easily identify the culprit? How to know what is done when? There must be some informations, logs, and so on... are there?
11-03-2020 12:40 PM
Hello, well as I am not allowed to share any code, there are some 2-3 loop statements in the code. The most "complicated" loop I found is something I put in pseudo code down below. Do not check for functionality as numbers might not match.
BUT as I said. I am looking for a way to not blindly suspect but to find where the synthesis got suck.
BTW: It might be a good idea to be able to insert VHDL code in a forum manly about HDL tools.
---- Pseudo Code ----
11-04-2020 01:06 AM
You have some large arrays and with some very complex logic chains because you used variables. I suspect this has something to do with it? Is the design synchronous? why cant it be pipelined?
Large logic chains in large arrays can cause these slowdowns. The code looks like its a re-write of some C code. This never leads to efficient HDL and likely to lead to timing and/or synthesis problems. Why cant you post the full code?
There is a "post code snippet" button in the toolbar
if you_want_to_post_some_code then use <= the_insert_code_button; end if;
11-04-2020 06:38 AM - edited 11-04-2020 06:39 AM
"Large logic chains in large arrays can cause these slowdowns."
While this is a valuable input, maybe my bad English is not allowing me to express the key element of my question good enough. I am looking for a way to identify sources of slow downs. While it is ok to be punished for bad coding, I was hoping that the tool (vivado) would give me information on where exactly it takes so long. My design right now is not really usable as it takes >8h to finish synthesis.
I am not primarily interested in you guys fishing for me, I am interested in learning to fish.
But to get there I need the means to identify current mistakes by my own, as I cant just always post my code here in the forum and then hope to get someone do my work.
11-04-2020 07:42 AM - edited 11-04-2020 07:42 AM
The tools will simply convert what you have written. They do not give style advice because they assume the designer is correct.
Here, the only way we can really help is to see the code. But from what Ive seen, Im suggesting it is not really very suitable HDL code. Have you read up on digitial logic design?
Is your design synchronous?
As a general rule to maximise efficiency you should only have a few luts between registers (the fewer you have, generally the faster it can go). From the code you posted, you're going to have 100s (or 1000s) of LUTs between regs (if there even is a clock). This is pretty bad.
Directly coverting C/Matlab code to HDL is usually going to produce a bad design.
Go back to your algorithm. Then draw on paper the circuit you expect to see. HDL is hardware description language. If you dont know what the circuit should be, then you have little hope of describing it with HDL.