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Visitor
Visitor
3,894 Views
Registered: ‎02-03-2016

SysGen - WARNING:Xst:1710

Hello everyone,

I am working with Xilinx System Generator (v 14.7) and I get this warning (linked to ALL addsub used blocks) when I generate the bitstream file. 

 

WARNING:Xst:1710 - FF/Latch <.../addsub/prev_mode_93_22_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[2].bit_is_0.fdre_comp> (without init value) has a constant value of 0 in block <..._cw>. This FF/Latch will be trimmed during the optimization process.

Simulink-based simulation works fine, but when I implement the design on the board, I get a very weired behaviour. That is why I ask you if tehre a solution to avoid/ignore this type of warning on the Sysgen Sythesis Task, since I don't have access to the addsub block architecture, neither the .ucf file.

 

Thank you very much!!

 

Yassine 

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Moderator
Moderator
3,846 Views
Registered: ‎07-21-2014

Re: SysGen - WARNING:Xst:1710

@yazi10

 

Did you verify these warnings and the signal connections in the design? I think the design does not have any valid connection for these signals and hence tool is removing them. You can use KEEP attribute on these signals in case you want to preserve them.

 

>> I get a very weired behaviour.

Regarding behaviour issue, try to check post-synth simulation results whether the issue is coming from synthesis or this is a timing related issue.

 

Thanks,
Anusheel
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Xilinx Employee
Xilinx Employee
3,842 Views
Registered: ‎05-07-2015

Re: SysGen - WARNING:Xst:1710

HI @yazi10

 

As advised, please do a post-translate or post -route simulation in ISE  and see if the same behavior on the board is repeating in  simulation. That way you can figure out if these warnings are relevant to the performance issue you are seeing.

Also, please share your slx/ mdl file if possible.

Thanks
Bharath
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