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simozz
Mentor
Mentor
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Registered: ‎05-14-2017

System Verilog for RTL synthesis in Vivado.

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Hello,

As UG901, Vivado supports System Verilog (SV) synthesis, but how can I choose SV as default language for RTL ?

From Vivado settings I can only set Verilog or VHDL as target language.

I tried to check if enum data type is automatically allowed in a Verilog file (for which enum is not supported) and Vivado failed to synthesize as expected.

Thanks.

s.

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aschule
Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎04-19-2010

There are a couple of ways to do this.  The first is to name your file with the .sv extension.  If you file is called something like test.sv, the tool will automatically compile it as SystemVerilog.  The second way is to set the file Type to SystemVerilog.  If you are in the GUI, right click on your file and select "Source File Properties".  In the properties window that comes up, there will be a field called "Type" with a "..." button next to it.  Click on that button and select SystemVerilog.

 

Going back to what you saw.  I believe that you were most likely in the Settings -> General window selecting the Target language.   This actually does not have an affect on the synthesis tool.  It actually controls the language that is generated for the simulation runs after synthesis runs.

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aschule
Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎04-19-2010

There are a couple of ways to do this.  The first is to name your file with the .sv extension.  If you file is called something like test.sv, the tool will automatically compile it as SystemVerilog.  The second way is to set the file Type to SystemVerilog.  If you are in the GUI, right click on your file and select "Source File Properties".  In the properties window that comes up, there will be a field called "Type" with a "..." button next to it.  Click on that button and select SystemVerilog.

 

Going back to what you saw.  I believe that you were most likely in the Settings -> General window selecting the Target language.   This actually does not have an affect on the synthesis tool.  It actually controls the language that is generated for the simulation runs after synthesis runs.

View solution in original post

simozz
Mentor
Mentor
180 Views
Registered: ‎05-14-2017

If you are in the GUI, right click on your file and select "Source File Properties".

Bingo ! This is useful for custom AXI cores created using Vivado wizard.

Thanks, @aschule.

s.

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