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Observer oft
Observer
2,049 Views
Registered: ‎07-03-2017

System verilog

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Hi

 

I work in a development team, and we have been using VHDL ever since the team was constructed. System verilog seems like a better lenguage for FPGA development - but as much as I have heard - is not supported enough to be used for development with the vivado design suite.

 

I wanted to know if that is really the case, and if so - is a better support planned for the next issues of VIVADO?

 

Also - how well do SV and VHDL work together? For legacy code usage.

 

thanks,

oft. 

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Moderator
Moderator
2,041 Views
Registered: ‎03-16-2017

Re: System verilog

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Hi @oft,

 

You can check UG 901 which shows the synthesizable Set of System Verilog 1800-2009 constructs which are supported in Vivado 2018.2 (which is the latest version today).

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf Page- 273, Chapter-8.

 

Regards,

hemangd

 

 

 

 

Regards,
hemangd

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Moderator
Moderator
2,042 Views
Registered: ‎03-16-2017

Re: System verilog

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Hi @oft,

 

You can check UG 901 which shows the synthesizable Set of System Verilog 1800-2009 constructs which are supported in Vivado 2018.2 (which is the latest version today).

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf Page- 273, Chapter-8.

 

Regards,

hemangd

 

 

 

 

Regards,
hemangd

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Advisor evgenis1
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Registered: ‎12-03-2007

Re: System verilog

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Hi @oft , 

 

>> but as much as I have heard - is not supported enough to be used for development with the vivado design suite.

>> I wanted to know if that is really the case, and if so - is a better support planned for the next issues of VIVADO?

 

That was true 4-5 years ago in early days of Vivado. That is not anymore: synthesizeable part of SystemVerilog is well supported.

 

Thanks,

Evgeni

 

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Scholar richardhead
Scholar
2,003 Views
Registered: ‎08-01-2012

Re: System verilog

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@oft

Why do you think this? VHDL is a perfectly good language to use, and can do anything SV can do (even in simulation). If you are already solid with VHDL - why spend all that time re-training?

 

 

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Historian
Historian
1,992 Views
Registered: ‎01-23-2009

Re: System verilog

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Vivado synthesis is actually surprisingly good with SystemVerilog - I have done several (complex) projects in SystemVerilog and have not recently come across a synthesizable construct that Vivado synthesis has a problem with.

 

I have less experience with the Vivado simulator (I mostly use 3rd party simulators). For a while, it was pretty clear that the subset supported by simulation was significantly less than what the synthesis tool supported (in fact there was a large period of time where there was no simulator support in spite of the fact that synthesis support was pretty far advanced).

 

As for SystemVerilog vs. VHDL, that is much more of a "religious" debate. At this point, both languages are well supported for synthesis and simulation.

 

The main drive pushing people toward SystemVerilog are the advanced verification methodologies like UVM and OVM (which are only supported in SystemVerilog). That being said

  - Vivado simulation does not support UVM/OVM

  - All 3rd party simulators support mixed VHDL/SystemVerilog simulations (for a price), which allows your verification to be done in SystemVerilog while your synthesizable RTL is still done in VHDL

 

So basically the choice remains yours - there is no compelling reason to switch from VHDL to SystemVerilog for design - except possibly for some value to having your Verification and Design Engineers working in the same language...

 

Avrum

Scholar richardhead
Scholar
1,980 Views
Registered: ‎08-01-2012

Re: System verilog

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@avrumw

 

Using something like OSVVM (open source vhdl verification methodology) gives you massive verification features in VHDL and the ability to use a single language licence.

 

SV (for verification) is a lot to learn when you already know VHDL. And UVM is another layer of complexity on top of that. Unless you have didicated verification engineers you likely wont have time to use it properly.

 

OSVVM is like a verification tool box and allows you to add more complexity as you feel comfortable. UVM generally feels more like an all or nothing environment.

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Historian
Historian
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Registered: ‎01-23-2009

Re: System verilog

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@richardhead,

 

I agree with you completely.

 

Adopting a new verification methodology is a VERY long term and very invasive/intensive process. It is definitely not one to be done lightly.

 

I do know that what you say is true - UVM requires a huge learning investment - mostly in terms of how you think about verification (rather than how you code verification). And, from what I know, you are right it is often an "all or nothing" kind of thing, and "all" takes a LOT of time to learn...

 

All that being said, UVM is a standard, and seems to be gaining in popularity - even in the FPGA community...

 

Avrum

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Scholar richardhead
Scholar
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Registered: ‎08-01-2012

Re: System verilog

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@avrumw

 

I have worked in a firmware team where we had dedicated verification engineers writing UVM testbenches. It did mean a lot of tests got specced at the start of the process and were written by very competent guys. It meant firmware bugfixes were about as low as Ive ever seen, and a lot of those were mostly due to poor specifications.

 

But when the redundancy axe was thrown, they were the first for the chop or redeployed onto firmware. It meant the testbenches were no longer getting written or maintained. It is VERY hard work for someone with only firmware development experience to navigate around an SV testbench, let alone UVM. (for a start, the OO used in SV is a new concept to most engineers used to hacking around with gates and probably some C for driver code).

 

While UVM is standardised and generally portable or extendable, I get the impression a lot of people want the tools capability without the complexity. While a lot of SV development houses will probably stick with SV for testbenches and might venture into UVM, there are plenty of tools to try and break the middle ground - things like OSVVM, UVVM in VHDL, then theres others like CocoTB, VUnit and MyHDL to allow python into the mix. I think all these offer great flexibility, and while they probably dont allow the huge range and compatability that UVM offer, they are likely easier for people to pick up, as they will all work with VHDL or Verilog.

Visitor lasplund
Visitor
1,803 Views
Registered: ‎08-25-2017

Re: System verilog

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@richardhead VUnit is more of a VHDL test framework than it is a tool trying to use Python for verification. It does come with a layer of Python scripting to handle the task of fully automating your test environment since that can't be done in VHDL alone but the utility packages for writing testbenches are still in VHDL and we also include OSVVM for its randomization features. It should also be noted that the Python based automation features also support testbenches written in SystemVerilog. There are even verification engineers using VUnit on top of UVM testbenches to get the full automation in place.
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Observer oft
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Registered: ‎07-03-2017

Re: System verilog

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Why did you say - python based verification technologies do not offer the same range and compatability that UVM offers?
For FPGA verification (not chip design) - it seems to me the two gives quite asimilar range of capabilities.

 

 

oft

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Visitor shivkumar1
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Registered: ‎05-16-2019

Re: System verilog

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System Verilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.

The feature-set of SystemVerilog can be divided into two distinct roles:

SystemVerilog for register-transfer level (RTL) design is an extension of Verilog-2005; all features of that language are available in SystemVerilog. Therefore, Verilog is a subset of SystemVerilog.
SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog. These constructs are generally not synthesizable.
The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.

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