While simulation works properly, the Vivado synthesis engine fails on inferring an intact MUX for indexing an `automatic` array.
This issue can be confirmed with Vivado 2020.1 with this example:
// Plain 4:1-MUX with named inputs a, b, c, d
module mux #(
type T = logic
)(
input logic clk,
input logic [1:0] s, // Select
input T a, b, c, d, // Data Inputs
output T y // Data Output
);
always_ff @(posedge clk) begin
automatic T src[4] = '{ 0: a, 1: b, 2: c, 3: d };
y <= src[s];
end
endmodule : mux
// Quick Testbench
module mux_tb;
typedef logic T;
logic clk = 0;
always #5ns clk = !clk;
// DUT
struct packed {
logic [1:0] s;
T [3:0] x;
} i;
T y;
mux dut(
.clk,
.s(i.s),
.a(i.x[0]), .b(i.x[1]), .c(i.x[2]), .d(i.x[3]),
.y
);
// Stimuli
initial begin
i = $urandom(42);
repeat(100) begin
@(posedge clk); #1ns;
$display("%0d of %04b -> %0x", i.s, i.x, y);
assert(y == i.x[i.s]) else begin
$error("Output mismatch.");
$stop;
end
i <= $urandom();
end
$finish;
end
endmodule : mux_tbWhile simulating `mux_tb` encounters no error, the synthesis will produce a severely impaired result completely ignoring three out of the four possible source inputs:
