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cjruggiero
Visitor
Visitor
2,895 Views
Registered: ‎02-01-2018

SystemVerilog invalid assignment pattern

I am working with a complex design using abstract data types and it is going well, for the most part.  I am using valid SV code for pattern assignment is resulting in an error with Vivado 2017.4.

 

[Synth 8-359] invalid assignment pattern ["E:/dev/projects/chiplib/cores/dport_tx/verilog/dptx_framing.sv":661]

 

If I define a struct as:

 

typedef struct {
    logic       a;
    logic [7:0] b;
} tSTRUCT_TYPE;

 

And define an input and signals as:

    input  tSTRUCT_TYPE        struct_in [3:0]
tSTRUCT_TYPE struct_use [3:0]
tSTRUCT_TYPE temp_0, temp_1, temp_2, temp_3

Then attempt a pattern assignment:

struct_use <= '{ struct_in[3], struct_in[2], struct_in[1], struct_in[0] };

Which results in an error.  The odd part is that if I remove the SV list assignment and make it a Verilog concatenation (remove the leading tick, that is), the code passes through okay.  A concatenation of unpacked structs doesn't seem right and I'm not confident that will get synthesized properly.  Please don't suggest a direct assignment, the actual code is more complicated than this example.

 

By using an intermediate assignment of the struct to a temp, this now passes through okay.

        // workaround for Vivado
        temp_0 = struct_in[0];
        temp_1 = struct_in[1];
temp_2 = struct_in[2];
temp_3 = struct_in[3];

struct_use <= '{ temp_3, temp_2, temp_1, temp_0 };

The above solution resolves the error but is not really feasible in this design given the number of places and how this is used.  We would need hundreds of new signals in the design.  In addition to the fact that hacking code is annoying and makes it less maintainable and more error prone.

 

We've tried most of the obvious modifications.  Any help would be appreciated.

 

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4 Replies
jmcclusk
Mentor
Mentor
2,888 Views
Registered: ‎02-24-2014

Hi @cjruggiero, this is definitely a bug in the SV parser/front end.   It's essential to submit a test case that can be thrown to the developers for verification and fixing this bug.   Can you throw together a quick demo of this bug and attach it to your post?  That will ensure that one of the Xilinx moderators will submit a CR (change request) quickly.

Don't forget to close a thread when possible by accepting a post as a solution.
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pulim
Xilinx Employee
Xilinx Employee
2,854 Views
Registered: ‎02-16-2014

Hi @cjruggiero

 

I am able reproduce this issue. Checking further to file a CR.

Will keep you posted.

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pulim
Xilinx Employee
Xilinx Employee
2,849 Views
Registered: ‎02-16-2014

Hi @cjruggiero

 

Filed CR-993914 for this issue.

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cjruggiero
Visitor
Visitor
2,832 Views
Registered: ‎02-01-2018

Thank you for getting this addressed so quickly.  We implemented a workaround by breaking up the assignments instead of using the list operator.  Not elegant but it works.

 

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