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Explorer
Explorer
1,060 Views
Registered: ‎04-01-2016

TCL command for inferring a DSP block

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Hi all,

 

I have to include a module from an ASIC colleague which is about adding 3 fixed points. Unfortunately in the ASIC there is no registering between the different steps and I am missing 0.3 ns.

 

My idea now is, that I can gain this time by inferring an DSP block for adding the 3 exponent values (which in fact are onle 8 bits wide, but as told, I just need 0.3 ns for each signal).

 

The VHDL code is the following:

res_exp <= s1_exp + s2_exp + s3_exp;

Previously I would have done the following way:

 

attribute use_dsp: string;
attribute use_dsp of res_exp : signal is ”true”;

But of course I'm not allowed to modify the ASIC sources. And I think it is better design style now to do with TCL. But I do not know the exact command. Furthermore I have the problem, that I cannot find the signal with the get_cells command after synthesis, I just see many carry stages.

 

In the thread TCL command for using a DSP block I found the following command which is exactly what I need.

set_property USE_DSP48 NO|YES [get_cells -hierarchical -filter { REF_NAME =~  "mult" } ]

But as told, my signal has gone. So Vivado already optimized a bit, but I hope that I can gain the 0.3 ns by inferring a DSP block. What are you thinking?

 

Thanks for helping!

Kind regards

Sebastian

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1 Solution

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Scholar jmcclusk
Scholar
1,527 Views
Registered: ‎02-24-2014

Re: TCL command for inferring a DSP block

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What FPGA technology are you using?   If it's a Series 7 device or above,  you should be able to do a ternary adder in a single stage of LUT logic.   Vivado does this, but it's NOT at all obvious from staring at the schematic..    I'll demonstrate... Here's the schematic for a 3 input, 8 bit adder, with 10 bit output..    Can you tell that this is being done in a single layer of logic?

 

ternary_adder.png

Just looking at the schematic,  you can't see it.  And with good reason..  in place and route, things get packed differently than you might expect, using the LUT6_2 cell with 2 outputs.  Down below is the layout for the bottom 4 bits of the ternary adder.  This uses a 3:2 compressor driving the binary adder fast carry logic, along with an extra carry bit that has to propagate to the next slice using ordinary routing.   The structure for this, strangely enough, is described in the DSP48E1 user guide (UG479, page 49).

 

ternary_adder_routed.png

In you have a ternary adder that's missing timing by 300 ps, and it's using this structure already,  there's very little you can do except enable retiming, in the hopes it will rob Peter to pay Paul for this setup time.    You can also attempt to modify placement by using TCL constraints on the driving signals,  trying to pull them closer to the outputs.  Floorplanning  *might* work.

Don't forget to close a thread when possible by accepting a post as a solution.
5 Replies
1,017 Views
Registered: ‎06-21-2017

Re: TCL command for inferring a DSP block

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I think that if you cannot use the registers in the DSP block, you will do no better, and probably worse than addition in fabric.  The only way you can do two additions in one DSP block is to make use of the preadder which is pretty hard to do without explicitly instantiating the DSP block, or using one of the Xilinx IPs that use the preadder such as the FIR filter compiler with symmetric coefficients.  Cascading two DSPs to get your two additions with no registers will also produce poor results.  I would be surprised if the synthesis tool even allows this.

Scholar markcurry
Scholar
1,013 Views
Registered: ‎09-16-2009

Re: TCL command for inferring a DSP block

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You could use a single DSP in SIMD mode to add (up to) 4, 12 bit values.  So it'd fit for the OP's requirements.

I've no good idea how to do it without modifying RTL, however. 

 

SIMD mode in the DSP48s is not availble via inference in any way, only instaciation...

 

The "no modifications" to RTL is really handcuffing you.  I can understand the base desire for this requirement.  But if done carefully, I'd think you'd have a path forward that was acceptable to all parties.

 

Good luck.

 

Regards,

 

Mark

Scholar jmcclusk
Scholar
1,528 Views
Registered: ‎02-24-2014

Re: TCL command for inferring a DSP block

Jump to solution

What FPGA technology are you using?   If it's a Series 7 device or above,  you should be able to do a ternary adder in a single stage of LUT logic.   Vivado does this, but it's NOT at all obvious from staring at the schematic..    I'll demonstrate... Here's the schematic for a 3 input, 8 bit adder, with 10 bit output..    Can you tell that this is being done in a single layer of logic?

 

ternary_adder.png

Just looking at the schematic,  you can't see it.  And with good reason..  in place and route, things get packed differently than you might expect, using the LUT6_2 cell with 2 outputs.  Down below is the layout for the bottom 4 bits of the ternary adder.  This uses a 3:2 compressor driving the binary adder fast carry logic, along with an extra carry bit that has to propagate to the next slice using ordinary routing.   The structure for this, strangely enough, is described in the DSP48E1 user guide (UG479, page 49).

 

ternary_adder_routed.png

In you have a ternary adder that's missing timing by 300 ps, and it's using this structure already,  there's very little you can do except enable retiming, in the hopes it will rob Peter to pay Paul for this setup time.    You can also attempt to modify placement by using TCL constraints on the driving signals,  trying to pull them closer to the outputs.  Floorplanning  *might* work.

Don't forget to close a thread when possible by accepting a post as a solution.
Explorer
Explorer
972 Views
Registered: ‎04-01-2016

Re: TCL command for inferring a DSP block

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Hi @bruce_karaffa, @markcurry and @jmcclusk

 

thank you very much for your posts! I expected / feared the same. So I think the only thing I can do is to lower the frequency.

 

Last week the ASIC department included pipelining registers in another module because I showed them the timing in the FPGA and after an ASIC synthesis they realized that it is also a problem in the ASIC.

 

For this module I hope the same. :)

 

Kind regards

Sebastian

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Explorer
Explorer
968 Views
Registered: ‎04-01-2016

Re: TCL command for inferring a DSP block

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@jmcclusk

 

Great job with the schematic and the logic! Thanks a lot!

 

Sebastian

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