03-25-2016 05:44 AM
As mentioned in the subject, I am trying to synthetize a design which is too large for the taget device (v6).
The problem is whithin the Number of RAMB36E1 used wich is 194% of existing. However, RAMB18E1 are only 1% used. I tried to use LUTs instead of BRAM but in this case, the synthesis is eternally stuck in a specific line of the mhs file which contains the Begin block of the IP.
I am wondering if it's possible to use RAMB18E1 or try something else to map correctly the design.
Thanks for your precious help !
03-25-2016 05:54 AM
Thank your for reply.
At first, I wasn't using the Ram style attribute and I got the error I talked about in my post. Then I tried using the attribute on mode "distributed" but the synthesis bloked.
03-25-2016 07:51 AM
There is a very confusing method with which block RAMs are reported in the usage statistics. In most newer parts, block RAM can be either 18Kb or 36Kb each. Each RAM block in the device can be configured as either 2 x 18Kb or 1 x 36Kb. However these block RAMs use the same resources. i.e. if you use all of the 36Kb BRAMs, there is no 18Kb RAM left, either. The tools, however report the 18Kb separately as if it were still available after being used up by the 36Kb blocks. The truth is that you have to take all 36Kb RAMs, then add 1/2 of the 18Kb RAMs in the design. That will tell you the total usage of 36K blocks. If it exceeds the number of 36K BRAMs in the part, then your design will not fit.
It is possible to gain some RAM using distributed RAM, however if you are over by 94% of available BRAM, this may be too much to fit in distributed memory.
05-26-2016 06:54 AM - edited 05-26-2016 07:04 AM
Thank you for your explanation.
It's clear for BRAM report.
I am still wondering if I can fin a way to implement my design because on my zc702 device it worked so I am curious why it didn't on virtex 6 while I think PL of virtex 6 is bigger than zynq.
I attached the map report for more details on the utlization.
Thank you a lot for helping.
05-30-2016 11:43 AM
The map report indicates that the Virtex 6 design is much larger than could possibly fit in the PL of the Zynq 7020. This seems to imply that you have changed the design. Have you added an embedded processor in the V6 version? If not, then the only possible conclusion is that the Zynq design was somehow using the PS memory as well as the PL memory. Can you post the map report for the Zynq design?
05-31-2016 01:20 AM