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Visitor
Visitor
525 Views
Registered: ‎06-21-2020

The submodule's port changed although flatten_hierarchy = none option selected

Dear Sir/Madam,

I found the vivado will change the submodule name although the flatten_hierarchy = none option is selected. The change will occur after the design is elaborate and before the synthesis. Could you please suggest how to keep the port of sub modules in the design.

 

Thanks!

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Xilinx Employee
Xilinx Employee
509 Views
Registered: ‎06-14-2018

Hi @shenglin ,

Could you please post snapshot of RTL and elaborated view that shows what exact has change.

You can apply (* keep_hierarchy = "yes" *) on module whose ports you want to retain.

Thanks,

Ajay

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Visitor
Visitor
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Registered: ‎06-21-2020

Hi, Ajay,

Yes, I have tried (* keep_hierarchy = "yes" *)  on the module, but at first it not take effect. I found there is some problem in the Vivado update function. When I update the rtl code, it seems the Vivado don't correct update the out of date information.

The version I am using is Vivado 2019.2 and the device is Zynq UltraScale+ ZCU104 Evaluation Board (xczu7ev-ffvc1156-2-e)

When I update the rtl, only synth_2 is out of date, but the design_1_AIoT_fpga_top_0_2_synth... is not out of date, so in fact the rtl file is not recompiled, and the change by add (* keep_hierarchy = "yes" *) don't take effect.

update.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2018

Hi @shenglin ,

Run design_1_AIoT_fpga_top_0_2_synth is OOC run, so unless you change configuration or RTL for that IP or related runs, it wont reflect that run as Out-of-date.

Here from snapshot looks like you have modified RTL for top level so only synth_1 is updated as Out-of-date.

In case you have added or removed port of OOC run, please check if you have got Warning for same. 

Please confirm if its other wise.

Thanks,

Ajay

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Are you going to modify RTL in the IP source files and rerun the IP OOC synth run?

-vivian

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Visitor
Visitor
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Registered: ‎06-21-2020

Hi, Ajay,

I did change the RTL related to it. Please see the hierarchy, my rtl change is in the hierarchy of PL part, which noted with red. After the change, the out of the context module runs don't out of date.

hier.png

 

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Visitor
Visitor
369 Views
Registered: ‎06-21-2020

Hi, Vivian,

Yes, in fact the IP is created from my RTL in the block design diagram. But when I have update the RTL, the IP don't out of date.

 

Best Regards!

Sheng

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Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎06-14-2018

Hi @shenglin ,

Just wanted to check did you made change in IP wrapper. If yes that wont make IP go out-of-date.

I see your have packaged RTL as IP. Try changing actual RTL of IP.

Thanks,

Ajay

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Visitor
Visitor
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Registered: ‎06-21-2020

Hi, Ajay,

 

I am not understand what is your mean " made change in IP wrapper", I just create it in block diagram with add_module command to add my PL top.

And I have checked the displayed location of rtl file in source window, it is the correct location.  

 

Best Regards!

Sheng

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Xilinx Employee
Xilinx Employee
319 Views
Registered: ‎06-14-2018

Hi @shenglin ,

I meant did you change connections in file marked in blue in image, that file is still a wrapper and not IP file.

If you change IP file , Run Report IP Status, if change IP is not available for Upgrade something is missing.

There could be muliple reasons

  •   It could not be packed correctly
  •   Packed in new repo that is not added to current vivado.

Please let us know your actual issue if its still  flatten_hierarchy = none changes port as in subject.

Thanks,

Ajay

 

 

snip1.JPG
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Visitor
Visitor
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Registered: ‎06-21-2020

Hi, Ajay,

I have changed the RTL file marked in blue. But after change, it don't out of date.

So in fact, it is not the issue about flatten_hierarchy = none problem, but out of date issues.

 

Best Regards!

Sheng

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