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polyee13
Explorer
Explorer
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Registered: ‎11-28-2011

Tristate IOBUF Infer vs. Instantiation

For some reason when coding tristates, the AXI EMC core signals don't get packed in the IOB (i.e. the EMC core constraints don't get applied), but when I instantiate the IOBUF they do. Anyone know why this is so?  We are using Synplify Pro Build: Synplify Pro (R) M-2017.03, Build 2626R, Feb 21 2017 and Vivado 2017.2. Our device is the V7 690T. The constraints for the EMC Core generated by Xilinx:

 

set_property IOB TRUE [get_cells U0/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_v_reg[*]]
set_property IOB TRUE [get_cells U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_o_reg_reg[*]]
set_property IOB TRUE [get_cells U0/EMC_CTRL_I/IO_REGISTERS_I/mem_cen_reg_reg[*]]

set_property IOB TRUE [get_cells U0/EMC_CTRL_I/IO_REGISTERS_I/mem_dq_t_reg_reg[*]]

 

See attachments for the two different coding styles.

Tags (3)
tristate_infer.JPG
tristate_instantiate_IOBUF.JPG
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anusheel
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Registered: ‎07-21-2014

@polyee13

 

Can you please share the snapshot of the netlist and also check for the warnings generated by Vivado.

 

Thanks,

Anusheel

 

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