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Trouble migrating BRAM from ISE to Vivado

Visitor
Posts: 6
Registered: ‎01-10-2014

Trouble migrating BRAM from ISE to Vivado

Hello all,

 

I am in the process of porting my design (https://github.com/gardners/c65gs) from ISE to Vivado.

 

I have hit a problem with the several BRAM memories that I have, which infer as BRAM just fine in ISE, but fail to do so in Vivado.  

 

Please see attached example of one of the memories.

 

I would prefer to continue inferring the memories rather than defining them using some other apporach, as it allows me to use the same VHDL for synthesis in Vivado and simulation in ghdl (I have some tools written around ghdl), as well as write scripts that pre-populate the various memories.

 

Any ideas what I am doing wrong?  

Is there a simple change I can make to enable BRAM inference to work?

 

Thanks in advance,

Paul.

Xilinx Employee
Posts: 920
Registered: ‎05-14-2008

Re: Trouble migrating BRAM from ISE to Vivado

[ Edited ]

Could you elaborate the problem of BRAM inference in Vivado? Is there any warning message? And what does Vivado finally infer from the RAM code?

 

And you can refer to the BRAM inference coding template in UG901. Compare your code to the templates and see if there is any difference?

 

-Vivian

Visitor
Posts: 6
Registered: ‎01-10-2014

Re: Trouble migrating BRAM from ISE to Vivado


viviany wrote:

Could you elaborate the problem of BRAM inference in Vivado? Is there any warning message? And what does Vivado finally infer from the RAM code?

 

And you can refer to the BRAM inference coding template in UG901. Compare your code to the templates and see if there is any difference?

 

-Vivian


I am just in the process of firing up my Vivado VM again so that I can get you the log file.

 

Thanks for the pointer to UG901, as I had tried Googling quite a bit to try to find information on inferring BRAM in Vivado.  A quick search for BRAM in that document shows single-port BRAM, true-port BRAM, and single-port ROM BRAM examples, but has nothing for simple dual-port (one read port one write port, but on different clocks), which is how my RAM is configured.

 

Irrespective of what that document says, there is a problem that the inference works fine in ISE, but not in Vivado.  Thus Vivado has a backwards-compatibility problem.  My understanding is that Vivado is supposed to be backward compatible with ISE.  Is this still the case?

 

I have the log file now & have attached the whole thing so that I don't accidently provide the wrong information.

 

You will see that the chipram RAM gets inferred as a massive array of RAM128, instead of RAMBs.  Interestingly, a couple of modules do get inferred as RAMBs, but most of the memories that infer as RAMB's just fine in ISE fail to do so in Vivado.  I can provide output from ISE as well, if only I could figure out where ISE logs information about RAM inference.  Tell me which output files from ISE, and I will happily provide them.

 

Thanks,

Paul.

Visitor
Posts: 6
Registered: ‎01-10-2014

Re: Trouble migrating BRAM from ISE to Vivado

Any further thoughts on what might be the cause of the problem?

 

If it helps, I can provide the complete project to allow for easy reproduction of the problem.

 

Thanks,

Paul.

Contributor
Posts: 32
Registered: ‎08-12-2008

Re: Trouble migrating BRAM from ISE to Vivado

I found a couple of errors in your ram file.  First, your type was declared as 9-bits wide, and the data busses are all 8-bits. 

 

Second, you appear to have a misunderstanding of blockram and distributed ram.  The first is synchronous, the second is not.  Your process is set up to be part asynchronous, part synchronous.  Not a good idea.  Many tools will not be able to handle it. 

 

You have the doutb as an asynchronous statement, outside of the if(clka), with addrb and ram in the sensitivity list.  If you want bram, you need to make that statement inside of the if(clka), and then addrb and ram do not need to be in the sensitivity list.

 

With the above changes, it implements as bram.  I've attached a modified version of your file.  Note the "read first" and "write first" commented lines.  Those should work, but I'm not 100% certain that Vivado handles the distinction.  Not sure if it matters in your application or not.