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Visitor
Visitor
5,283 Views
Registered: ‎10-23-2016

Trouble with test bench for my first mux 4-1

I am new to VHDL and coding in general. The lab for my freshmen class is to design a 4-to-1 multiplexer. We designed a 2-to-1 multiplexer last week but this 4-to-1 multiplexer has proven to be a bit more complicated. I can get my input A to be mirrored as output y in the timing diagram but I would like to figure out how to get all the inputs functioning. This is my source code,

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end mux4_1;
architecture Behavioral of mux4_1 is
component Lab_6_4_to_1_Source_Code is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal p,q : STD_LOGIC_VECTOR (3 downto 0);
begin
M1: Lab_6_4_to_1_Source_Code port map (a=>A, b=>B, s=>S(0), y=>p);
M2: Lab_6_4_to_1_Source_Code port map (a=>C, b=>D, s=>S(0), y=>q);
M3: Lab_6_4_to_1_Source_Code port map (a=>p, b=>q, s=>S(1), y=>Y);
end behavioral;

 

And this is my test bench code,

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Lab_6_TB is
end Lab_6_TB;
architecture Behavioral of Lab_6_TB is
component mux4_1 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal A : STD_LOGIC_VECTOR (3 downto 0);
signal B : STD_LOGIC_VECTOR (3 downto 0);
signal C : STD_LOGIC_VECTOR (3 downto 0);
signal D : STD_LOGIC_VECTOR (3 downto 0);
signal S : STD_LOGIC_VECTOR (1 downto 0);
signal Y : STD_LOGIC_VECTOR (3 downto 0);
begin
UUT: mux4_1 port map (A=>A, B=>B, C=>C, D=>D, S=>S, Y=>Y);
process
begin
A<="0000"; B<="0000"; C<="0000"; D<="0000"; S<="00";
wait for 20 ns;
for i in 1 to 15 loop A <=A+1;
wait for 20 ns;
--wait for 1310720 ns;
--for i in 1 to 15 loop A <=A+1;
--wait for 81920 ns for i in 1 to 15 loop B <=B+1;
--wait for 5120 ns for i in 1 to 15 loop C <=C+1;
--wait for 320 ns for i in 1 to 15 loop D <=D+1;
--wait for 20 ns for i in 1 to 3 loop S <=S+1;
--wait for 5 ns;
end loop;
end process;
end Behavioral;

 

A couple of us in the lab thought the loop statement that we learned a few weeks ago might be able to get everything firing but we haven't had any luck with it. The commented lines are just my most recent attempt and they didn't work. Could anyone please help? Thank you.

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5 Replies
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Xilinx Employee
Xilinx Employee
5,256 Views
Registered: ‎08-01-2008

Re: Trouble with test bench for my first mux 4-1

check these third party example

http://teahlab.com/VHDL_Code_4_to_1_Line_Multiplexer/
http://vhdlguru.blogspot.in/2010/03/simple-4-1-multiplexer-using-case.html
Thanks and Regards
Balkrishan
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Highlighted
Visitor
Visitor
5,242 Views
Registered: ‎10-23-2016

Re: Trouble with test bench for my first mux 4-1

Thank you. I will check that out and see what I can come up with.

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Professor
Professor
5,233 Views
Registered: ‎08-14-2007

Re: Trouble with test bench for my first mux 4-1

It's hard to tell what you had with the commented out lines.  In any case you need to do your loops sequentially, not have one loop inside the other.  This isn't VHDL, just an idea of the algorithm:

 

set A, B, C, D, S to all zeroes.

loop through all possible values of A with some delay after each iteration (like 20 ns)

set S to "01"

loop through all possible values of B with some delay after each iteration (like 20 ns)

set S to "10"
loop through all possible values of C with some delay after each iteration (like 20 ns)

set S to "11"
loop through all possible values of D with some delay after each iteration (like 20 ns)

 

-- Gabor
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Highlighted
Visitor
Visitor
5,214 Views
Registered: ‎10-23-2016

Re: Trouble with test bench for my first mux 4-1

Yes, that is what I'm trying to do. I just can't figure out how to turn that into VHDL. My commented lines were my attempt stage different delay times to allow all the processes to run but it didn't work. This is my latest attempt but it just has all of the ports as undefined,

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Lab_6_TB is
end Lab_6_TB;
architecture Behavioral of Lab_6_TB is
component mux4_1 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal A : STD_LOGIC_VECTOR (3 downto 0);
signal B : STD_LOGIC_VECTOR (3 downto 0);
signal C : STD_LOGIC_VECTOR (3 downto 0);
signal D : STD_LOGIC_VECTOR (3 downto 0);
signal S : STD_LOGIC_VECTOR (1 downto 0);
signal Y : STD_LOGIC_VECTOR (3 downto 0);
begin
UUT: mux4_1 port map (A=>A, B=>B, C=>C, D=>D, S=>S, Y=>Y);
process
begin


S<="00"; A<="0000";B<="0000";C<="0000";D<="0000";
wait for 20 ns;
for i in 1 to 15 loop(4) A<=A+1;
wait for 20 ns;
end loop(4);
S<="01";
C<="0000";
wait for 20 ns;
for i in 1 to 15 loop(3) B<=B+1;
wait for 20 ns;
end loop(3);
S<="10";
C<="0000";
wait for 20 ns;
for i in 1 to 15 loop(2) C<=C+1;
wait for 20 ns;
end loop(2);
S<="11";
D<="0000";
wait for 20 ns;
for i in 1 to 15 loop(1) D<=D+1;
wait for 20 ns;
end loop(1);

end process;
end Behavioral;

 

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Highlighted
Visitor
Visitor
5,128 Views
Registered: ‎10-23-2016

Re: Trouble with test bench for my first mux 4-1

I found a classmate that figured it out. This is it,

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Lab_6_TB is
end Lab_6_TB;
architecture Behavioral of Lab_6_TB is
component mux4_1 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal A : STD_LOGIC_VECTOR (3 downto 0);
signal B : STD_LOGIC_VECTOR (3 downto 0);
signal C : STD_LOGIC_VECTOR (3 downto 0);
signal D : STD_LOGIC_VECTOR (3 downto 0);
signal S : STD_LOGIC_VECTOR (1 downto 0);
signal Y : STD_LOGIC_VECTOR (3 downto 0);
begin
UUT: mux4_1 port map (A=>A, B=>B, C=>C, D=>D, S=>S, Y=>Y);
process begin A<="0000"; wait for 81920 ns;
for i in 1 to 15 loop A<=A+1; wait for 81920 ns; end loop;
end process;
process begin B<="0000"; wait for 5120 ns;
for i in 1 to 15 loop B<=B+1; wait for 5120 ns; end loop;
end process;
process begin C<="0000"; wait for 320 ns;
for i in 1 to 15 loop C<=C+1; wait for 320 ns; end loop;
end process;
process begin D<="0000"; wait for 20 ns;
for i in 1 to 15 loop D<=D+1; wait for 20 ns; end loop;
end process;
process begin S<="00"; wait for 320 ns;
for i in 1 to 3 loop S<=S+1; wait for 320 ns; end loop;
end process;
end Behavioral;

 

I know there are other ways to do it but this accomplishes what I needed to. Thank you for all the suggestions. Since we were instruction to design our 4-to-1 multiplexer in a different manner than most others it made finding help difficult. 

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