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Visitor
Visitor
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Registered: ‎06-04-2018

True Dual Port Asymmetric RAM Write First (Verilog)

As I was reading the UG901, I noticed that on page 138 in the True Dual Port Asymmetric RAM Write First (Verilog) section, the code was written as

always @(posedge clkB)
begin
if (enaB) begin
if (weB)
RAM[addrB] = diB;
readB = RAM[addrB] ;
end
end
assign doutb = readB
To my understanding, the blocking assignment here is used for the write-first mode. My question is very simple, why using the top method instead of the bottom one? Is there a specific reason for that?
I guess the top method will introduce a small delay between diB and doutb, is that right?
always @(posedge clkB)
begin
if (enaB) begin
if (weB)
RAM[addrB] <= diB;
doutb <= diB ;
end
end
 
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Highlighted
Scholar
Scholar
579 Views
Registered: ‎08-07-2014

@mengjiuxi,

Simulate and synthesize both models. You will get your answer. :-)

 

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