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Scholar richardhead
Scholar
1,220 Views
Registered: ‎08-01-2012

UG901 - VHDL 2008 - Case? description, bad wording and incorrect example

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Just having a look through VHDL 2008 section of UG901:

 

With VHDL-2008, the case statement has a way to deal with explicit don’t care assignments. When using case?, the tool now evaluates explicit don’t cares, as in the following example:

process(clk) begin
  if clk’event and clk=’1’ then
    case? my_reg is 
      when “11--“ => out1 <= in1; 
      when “000-“ => out1 <= in2; 
      when “1111” => out1 <= in3;
      when others => out1 <= in4; 
    end case? 
  end if; 
end process;

Note: For this statement to work, the signal in question must be assigned an explicit don’t care.

 

It is this note at the end that is confusing? which signal is it refering to? the whole point of case? and select? is that the signal  (my_reg in this case) should NOT use explicit dont cares, but the cases do (as illustrated above). The problem in VHDL 1993 was that if you used dont cares in the cases, then the signal MUST have explicit dont cares in them. VHDL 2008 allows matching the dont cares to '0' or '1'.

 

Also, the demo is wrong. The code will not compile as the "1111" is already covered by the "11--" case, and VHDL rules mean that in a case or case?, each condition MUST be covered exactly ONCE only. case? is mainly to aid in address decoding, like this:

 

case? addr is
  when "0---" => -- covers all addresses 0x0 to 0x7
  when "10--" => -- covers 0x8 to 0xB
  when "110-" => -- 0xC to 0xD
  when "111-" => -  0xE to 0xF
when others => report "Addr contains U, Z or X values" severity failure; end case?;

 

1 Solution

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Xilinx Employee
Xilinx Employee
1,645 Views
Registered: ‎02-16-2014

Re: UG901 - VHDL 2008 - Case? description, bad wording and incorrect example

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Hi @richardhead

 

Filed CR#993256 for Vivado synthesis to provide error for this code and CR#993179 to correct the typos.

Document will be updated in future releases.

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3 Replies
Scholar richardhead
Scholar
1,211 Views
Registered: ‎08-01-2012

Re: UG901 - VHDL 2008 - Case? description, bad wording and incorrect example

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Also, another error:

in case..generate, -> is used instead of =>
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Xilinx Employee
Xilinx Employee
1,188 Views
Registered: ‎02-16-2014

Re: UG901 - VHDL 2008 - Case? description, bad wording and incorrect example

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Hi @richardhead

 

Thanks for your post. I will report this issue to factory.

 

Regards,

Manusha

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Xilinx Employee
Xilinx Employee
1,646 Views
Registered: ‎02-16-2014

Re: UG901 - VHDL 2008 - Case? description, bad wording and incorrect example

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Hi @richardhead

 

Filed CR#993256 for Vivado synthesis to provide error for this code and CR#993179 to correct the typos.

Document will be updated in future releases.

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