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Advisor ronnywebers
Advisor
7,261 Views
Registered: ‎10-10-2014

UG901 - distributed vs block ram inference

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UG901 gives templates for distributed RAM inference and block ram inference. 

 

I'm wondering what difference in the code makes the synthesis engine decide to infer distributed vs block ram - is it only determined by the size of the array?

 

distributed RAM example :

 

-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_dist is
	port(
		clk : in  std_logic;
		we  : in  std_logic;
		a   : in  std_logic_vector(5 downto 0);
		di  : in  std_logic_vector(15 downto 0);
		do  : out std_logic_vector(15 downto 0)
	);
end rams_dist;

architecture syn of rams_dist is
	type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0);
	signal RAM : ram_type;
begin
	process(clk)
	begin
		if (clk'event and clk = '1') then
			if (we = '1') then
				RAM(conv_integer(a)) <= di;
			end if;
		end if;
	end process;

	do <= RAM(conv_integer(a));

end syn;

block ram example :

 

-- Block RAM with Resettable Data Output
-- File: rams_sp_rf_rst.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_sp_rf_rst is
	port(
		clk  : in  std_logic;
		en   : in  std_logic;
		we   : in  std_logic;
		rst  : in  std_logic;
		addr : in  std_logic_vector(9 downto 0);
		di   : in  std_logic_vector(15 downto 0);
		do   : out std_logic_vector(15 downto 0)
	);
end rams_sp_rf_rst;

architecture syn of rams_sp_rf_rst is
	type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0);
	signal ram : ram_type;
begin
	process(clk)
	begin
		if clk'event and clk = '1' then
			if en = '1' then            -- optional enable
				if we = '1' then        -- write enable
					ram(conv_integer(addr)) <= di;
				end if;
				if rst = '1' then       -- optional reset
					do <= (others => '0');
				else
					do <= ram(conv_integer(addr));
				end if;
			end if;
		end if;
	end process;

end syn;
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Moderator
Moderator
10,592 Views
Registered: ‎11-09-2015

Re: UG901 - distributed vs block ram inference

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Hi @ronnywebers,

 

It also take in account the resources available, the timing...

 

The array size is the main parameter is because you don't want do loose block RAM resources (not really scalable).

 

With a block RAM you can have 18kB but not less (or it will be wasted).

 

While distributed RAM (in one CLBs) can be configured a follow:

RAM.JPG

 

For information, you can tell the synthesis tool what type of memory you want to use for each array with the RAM_STYLE synthesis attribute:

example:

attribute ram_style : string;
attribute ram_style of myram : signal is "distributed";

 

Hope that helps,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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9 Replies
Xilinx Employee
Xilinx Employee
7,250 Views
Registered: ‎08-01-2008

Re: UG901 - distributed vs block ram inference

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its depends upon attribute ram_style, rom_style
https://www.xilinx.com/support/answers/54778.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Moderator
Moderator
10,593 Views
Registered: ‎11-09-2015

Re: UG901 - distributed vs block ram inference

Jump to solution

Hi @ronnywebers,

 

It also take in account the resources available, the timing...

 

The array size is the main parameter is because you don't want do loose block RAM resources (not really scalable).

 

With a block RAM you can have 18kB but not less (or it will be wasted).

 

While distributed RAM (in one CLBs) can be configured a follow:

RAM.JPG

 

For information, you can tell the synthesis tool what type of memory you want to use for each array with the RAM_STYLE synthesis attribute:

example:

attribute ram_style : string;
attribute ram_style of myram : signal is "distributed";

 

Hope that helps,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Visitor alexmxlr
Visitor
7,201 Views
Registered: ‎06-29-2017

Re: UG901 - distributed vs block ram inference

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The main difference between these two code examples is that memory output is driven directly in the first one and clocked out in the second. By using the memory output in the same clock as the supplied address, you are forcing the tools to go distributed regardless of the size because block ram can't do that. If you use block ram template with properly clocked out output (not sure about the part where the output is reset to zero - looks dodgy to me), then you can leave it to the tools to decide or force it with an attribute.

 

Alex

 

Moderator
Moderator
7,158 Views
Registered: ‎11-09-2015

Re: UG901 - distributed vs block ram inference

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Hi @alexmxlr,

 

Where your explaination is coming from?

 

Just look at the templates from vivado to instantiate a block RAM:

process(clka)
begin
    if(clka'event and clka = '1') then
        if(wea = '1') then
            ram_name(to_integer(unsigned(addra))) <= dina;
        end if;
        if(enb = '1') then
            ram_data <= ram_name(to_integer(unsigned(addrb)));
        end if;
    end if;
end process;

--  Following code generates LOW_LATENCY (no output register)
--  Following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing

no_output_register : if C_RAM_PERFORMANCE = "LOW_LATENCY" generate
    doutb <= ram_data;
end generate;

If you don't select an output register, this is what you have.

 

Also just look at the figure 1-2 of the UG473:

BRAM.JPG

 

The output is not clocked.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor alexmxlr
Visitor
7,144 Views
Registered: ‎06-29-2017

Re: UG901 - distributed vs block ram inference

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@florentw

 

You are correct, 7-series and Ultrascale BRAMs got a so-called "latch" mode. I never use unbuffered memory output so my knowledge here got obsolete. Though there are plenty of devices prior to 7-series still in use.

 

Regards,

Alex

 

Moderator
Moderator
7,138 Views
Registered: ‎11-09-2015

Re: UG901 - distributed vs block ram inference

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Hi @alexmxlr,

 

Though there are plenty of devices prior to 7-series still in use

-> I agree but this is for UG901 -> vivado -> so at least 7-series

 

Thank you for participating on the community forums.

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor tmacqui
Visitor
1,017 Views
Registered: ‎02-14-2019

Re: UG901 - distributed vs block ram inference

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Hello,

Can I use a single inference to create Block RAMs which are larger than the basic block RAM sizes?

for example:

entity rams_sp_rf_rst is
port(
         clk : in std_logic;
         en : in std_logic;
         we : in std_logic;
         rst : in std_logic;
         addr : in std_logic_vector(15 downto 0);
         di : in std_logic_vector(7 downto 0);
         do : out std_logic_vector(7 downto 0)
);
end rams_sp_rf_rst;

architecture syn of rams_sp_rf_rst is
         type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0);
         signal ram : ram_type;
begin

       .....same code body......

end syn;

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Scholar markcurry
Scholar
1,007 Views
Registered: ‎09-16-2009

Re: UG901 - distributed vs block ram inference

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Yes.  

I've been meaning to play around with various sizes to see how synthesis puts together multiple Block Rams in order to for the aggregate array.  But never have the time to run the experiments..

Just try it, it'll work fine.

Regards,

Mark

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Visitor tmacqui
Visitor
959 Views
Registered: ‎02-14-2019

Re: UG901 - distributed vs block ram inference

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Hello,

The VHDL behavioral example provided (64kx8) produces an array of block RAM. 

-Tom

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