07-31-2019 06:37 AM
I am trying to tune the implementation of a URAM-based memory instantiated via the XPM_MEMORY_SDPRAM. Seems like the only knob I have for tuning the performance is the READ_LATENCY_B, which allows Vivado to apply some mix of output data and input data/control pipelining (of its own choosing).
Is there a way to more precisely control the pipelining/matrix properties, without resorting to manually creating an array of URAM288 primitives?
07-31-2019 08:16 PM
READ_LATENCY_B ensures you pipeline requirment in a way to improve timing performance as much as possible.
Do you encounter any suboptimal implementation?
08-01-2019 05:57 AM
Yes, I see suboptimal implementation. E.g. the specified latency appears to first go into building out output pipeline, then pipelining inputs - even though in my case the inputs seem to be in the critical path.
I do build very deep structures - 128/256 URAMs deep