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Visitor
Visitor
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Registered: ‎05-08-2018

Unable to initialize shift register. Gets optimized away

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My design has a rotating shift register containing constants. It's supposed to shift a value out on one side and the same one in again on the other side, and there is one tap to output a constant. In simulation it works exactly as expected. In synthesis I expected SRLs, but the whole thing gets optimized away and the output connected to ground. I don't understand why.

It seems to be related to the registers all being initialized to 0. I tried both initializing them using an initial value within the declaration, as well as using an "initial" statement. Neither works.

module coeff_srl #(parameter data_width = 16)(
  input  clk,
  input  en,
  output [data_width-1 : 0] P5_coeff
);

localparam order = 48;
localparam s = 2**data_width; // scaling factor

reg [data_width-1:0] shift_reg[0:order-1] = {
  s*0.0012, s*0.0014, s*0.0018, s*0.0024, s*0.0032, s*0.0043, s*0.0057, s*0.0074,
  s*0.0095, s*0.0118, s*0.0143, s*0.0171, s*0.0201, s*0.0232, s*0.0263, s*0.0294,
  s*0.0324, s*0.0353, s*0.0379, s*0.0402, s*0.0421, s*0.0436, s*0.0446, s*0.0451, 
  s*0.0451, s*0.0446, s*0.0436, s*0.0421, s*0.0402, s*0.0379, s*0.0353, s*0.0324,
  s*0.0294, s*0.0263, s*0.0232, s*0.0201, s*0.0171, s*0.0143, s*0.0118, s*0.0095,
  s*0.0074, s*0.0057, s*0.0043, s*0.0032, s*0.0024, s*0.0018, s*0.0014, s*0.0012  
};

genvar i;
generate
  for (i=0; i < order - 1; i++) begin
    always_ff @(posedge clk) begin
      if (en) shift_reg[i] <= shift_reg[i+1];
    end;
  end;
endgenerate;

always_ff @(posedge clk) begin
  if (en) shift_reg[order-1] <= shift_reg[0];
end;

assign P5_coeff = shift_reg[0];

endmodule

 

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Highlighted
Visitor
Visitor
335 Views
Registered: ‎05-08-2018

I can confirm this is a bug with Vivado 2018.2.

In Vivado 2019.2 it is fixed.

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-14-2018

Hi @dbemmann 

I see SRLs inferred. I have used latest released 2019.2.


Capture.JPG

What Vivado version are you using ?

 

Thanks,

Ajay 

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Visitor
Visitor
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Registered: ‎05-08-2018

I am using Vivado v2018.2 (64-bit) SW Build: 2258646.

I was considering using the ARM Cortex M1 softcore and according to Adam Taylor's webinar on it, it works only with v2018.2. Now since I'm not going to use that core anymore, I will try upgrading to 2019.2.

Still it's strange that synthesis would not recognize initialization of a 2D array in a build that is only a year and a half old. Am I using the correct syntax? The synthesis guide only has examples for initializing 1D vectors and RAMs.

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Visitor
Visitor
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Registered: ‎05-08-2018

I can confirm this is a bug with Vivado 2018.2.

In Vivado 2019.2 it is fixed.

View solution in original post

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