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Participant
Participant
1,165 Views
Registered: ‎05-17-2018

Unconnected net in RTL schematic

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Hi, I often have a problem with the RTL schematics of mealy FSMs, such as the simple one described in the following example:

process(clk)
begin
	if rising_edge(clk) then
		case state is

			when idle =>
				counter <= counter + 1;
				if counter = 2 then
					state <= read_val;
				end if;

			when read_val =>
				counter <= counter + 1;
				if counter = 15 then
					state <= next_val;
					counter <= 0;
				end if;

			when next_val =>
				state <= idle;

		end case;
	end if;
end process;

process(state)
begin

	case state is

		when read_val =>
			buff_wr <= '1';

		when others =>
			buff_wr <= '0';

	end case;
end process;

In short, I have tree states with state transitions determined by a counter, and "buff_wr" signal used to enable a FIFO. In this example buff_wr should be '1' only during the read_val state.

In the resulting RTL schematic the buff_wr signal, while properly generated, is not connected to the fifo (event_ff), which have its wr_en signal tied to ground.

RTL SchematicRTL Schematic 

I don't get any errors or warnings during synthesis and the synthesis schematics looks correct:

Synth schematicSynth schematic

Looking around I found some posts reporting a similar behaviour in the older ISE toolchain (apparently caused by a bug), but I was not able to find any similar reports for vivado (I'm using the 2018.2 version). So I was wondering If there was something wrong with my codestyle, since I often see similar issues with signals generated by asychronous processes.

I should also add that the RTL schematic is generated properly if I remove the last state (next_val) and skip directly to idle.

 

Thank you for any help you can provide.

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Participant
Participant
736 Views
Registered: ‎05-17-2018

well, I updated to vivado 2019.1 this morning (coming from 2018.2) and I no longer have this issue. I'm guessing it was more some kind of bug of the RTL viewer than something wrong with the code.

View solution in original post

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8 Replies
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Moderator
Moderator
1,112 Views
Registered: ‎03-16-2017

Hi @john ,

Can you provide the full testcase and elaboration of your question in details to investigate this issue? 

I can see that buff_wr mux output is trimmed. But need to investigate it further.

Regards,
hemangd

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Participant
Participant
1,101 Views
Registered: ‎05-17-2018

Hi, not sure what you mean by full elaboration, I am attaching a simple testcase that fully reproduces the issue on my system.

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Moderator
Moderator
1,034 Views
Registered: ‎03-16-2017

Hi @john ,

I am addressing the main issue here which you are talking about that buff_wr output is unconnected and needs to be connected to wr_en in elaborated design. 

I have modified your RTL and made a single sequentlal block for FSM which resolves your above mentioned query. Code is attached here. Try it at your end.

Regards,
hemangd

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Participant
Participant
1,018 Views
Registered: ‎05-17-2018

Thank you for your answer. I know I can fix this problem by using a synchronous design, my doubt is why I get that result with an asynchronous process, especially since it seems that I get the correct result after synthesis.

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Moderator
Moderator
1,007 Views
Registered: ‎03-16-2017

Hi @john ,

>> it seems that I get the correct result after synthesis.

Are you able to see buff_wr in synthesized design? Is your functionality correct in post synthesis simulation? 

 

Because, It is visible with synchronous design, single synchronous block as shown below. 

buff_wr.JPG 

 

Regards,
hemangd

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Participant
Participant
984 Views
Registered: ‎05-17-2018

yes, as also shown in the second picture in the first post I can see the signal in the synthesized design. It also behaves properly in the post synth simlation. It's not connected only in the RTL schematic.

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Participant
Participant
737 Views
Registered: ‎05-17-2018

well, I updated to vivado 2019.1 this morning (coming from 2018.2) and I no longer have this issue. I'm guessing it was more some kind of bug of the RTL viewer than something wrong with the code.

View solution in original post

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Xilinx Employee
Xilinx Employee
712 Views
Registered: ‎05-14-2008

Please accept your own answer as solution to close this thread.

Thanks

-vivian

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