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Newbie
Newbie
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Registered: ‎01-15-2016

Understanding/Solving Synth 8-4480 "The timing (...)"

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When I synthesize my design an information-warning appears saying:

 

"[Synth 8-4480] The timing (...) (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing."

 

How can I address this?

 

The code for my RAM follows below:

 

module ram(
            input clock, // System clock
            input we, // When high RAM sets data in input lines to given address
            input [13:0] data_in, // Data lines to write to memory
            input [10:0] addr_in, // Address lines for saving data to memory
            input [10:0] addr_out, // Address for reading from ram
            output reg [13:0] data_out // Data out
    );
    
    reg [13:0] ram[2047:0]; // Stored data
    
    parameter FILE_PATH = ""; // Path to initialization file
    
    // Initialize RAM from file
    initial begin
        if (FILE_PATH != "") begin
            $readmemh(FILE_PATH,ram);
        end
    end        
    
    always @(posedge clock) begin
        // Save data to RAM
        if (we) begin
            ram[addr_in] <= data_in;
        end
        
        // Place data from RAM
        data_out <= ram[addr_out];
    end    
    
endmodule
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Guide
Guide
15,846 Views
Registered: ‎01-23-2009

This doesn't necessarily need to be addressed.

 

The block RAMs in Xilinx FPGAs have two output modes. The normal output mode has a one clock latency (the data is available on the cycle after the address is provided), but the data arrives fairly late in the clock period, which can make it hard to meet timing between the output of the RAM and the logic that is driven by the RAM.

 

In the other mode, you enable the "output registers" on the RAM. In this case, the read latency is 2 clocks; the data becomes available on the 2nd clock after the address is provided. However, in this mode, the data arrives early in the (2nd) clock period, making it easier to meet timing between the output of the RAM and the data it is driving.

 

When you infer a RAM, the tools look to see if the read logic is immediately followed by another flip-flop. If so, this flip-flop will be packed (merged) into the RAM, putting the RAM into the "output register" mode. In  your code, there is no such register, so the tools are merely saying that it is using the one clock latency mode, which has a long clock to output.

 

If you can meet timing like this, then there is nothing to do.

 

Avrum

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1 Reply
Highlighted
Guide
Guide
15,847 Views
Registered: ‎01-23-2009

This doesn't necessarily need to be addressed.

 

The block RAMs in Xilinx FPGAs have two output modes. The normal output mode has a one clock latency (the data is available on the cycle after the address is provided), but the data arrives fairly late in the clock period, which can make it hard to meet timing between the output of the RAM and the logic that is driven by the RAM.

 

In the other mode, you enable the "output registers" on the RAM. In this case, the read latency is 2 clocks; the data becomes available on the 2nd clock after the address is provided. However, in this mode, the data arrives early in the (2nd) clock period, making it easier to meet timing between the output of the RAM and the data it is driving.

 

When you infer a RAM, the tools look to see if the read logic is immediately followed by another flip-flop. If so, this flip-flop will be packed (merged) into the RAM, putting the RAM into the "output register" mode. In  your code, there is no such register, so the tools are merely saying that it is using the one clock latency mode, which has a long clock to output.

 

If you can meet timing like this, then there is nothing to do.

 

Avrum

View solution in original post