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Observer roader
Observer
772 Views
Registered: ‎10-14-2015

Understanding how blocking and non blocking statements work in this AXI4 interface

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Hi,

 

I am looking at a small AXI4 interface block and am trying to understand how the synthesis tool handles the always@* logic and what it actually synthesizes to.

 

This is what the code which I am going through looks like.

 

always @* begin 
    write = 1'b0;  
  
    wr_ptr_next = wr_ptr_reg;  
    wr_ptr_gray_next = wr_ptr_gray_reg;  
  
    if (s00_axis_tvalid) begin  
        // input data valid  
        if (~full) begin  
            // not full, perform write  
            write = 1'b1; 
            wr_ptr_next = wr_ptr_reg + 1; 
            wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); 
        end 
    end 
end 
 
always @(posedge s00_axis_aclk) begin 
    if (s00_rst_sync3_reg) begin 
        wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};  
        wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; 
    end else begin 
        wr_ptr_reg <= wr_ptr_next; 
        wr_ptr_gray_reg <= wr_ptr_gray_next; 
    end 
 
    wr_addr_reg <= wr_ptr_next; 
 
    if (write) begin 
        mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data; 
    end 
end 

 

The code is taken from alex forencich's github repository located here https://github.com/alexforencich/verilog-axis.

 

The above snippet is trying to generate the write address for the RAM. I am still a little confused as to how the always@* synthesized to. In the above example each time the block is entered write is set to 0, then write pointer next is incremented and the incremented value is used to generate the gray code address. Could someone explain how the always@* logic works? What is it synthesizing to in hardware?

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1 Solution

Accepted Solutions
Explorer
Explorer
1,074 Views
Registered: ‎09-07-2011

Re: Understanding how blocking and non blocking statements work in this AXI4 interface

Jump to solution

Well, you can synthesize it in Vivado and have a look..

 

But in general, the always @* will create combinational logic... so ANDs and ORs and not flip-flops.

 

The "if" statements will produce something equivalent to a mux.

 

Not sure if this helps, but it's equivalent to this (slightly more hardware looking) snippet:

 

wire  mux_select = s00_axis_tvalid & (~full);

wire write = (mux_select==1)? 1 : 0 ; wire wr_ptr_next = (mux_select==1)? wr_ptr_reg + 1 : wr_ptr_reg; wire wr_ptr_gray_next = (mux_select==1)? wr_ptr_next^(wr_ptr_next>>1) : wr_ptr_gray_next;

 

 

2 Replies
Explorer
Explorer
1,075 Views
Registered: ‎09-07-2011

Re: Understanding how blocking and non blocking statements work in this AXI4 interface

Jump to solution

Well, you can synthesize it in Vivado and have a look..

 

But in general, the always @* will create combinational logic... so ANDs and ORs and not flip-flops.

 

The "if" statements will produce something equivalent to a mux.

 

Not sure if this helps, but it's equivalent to this (slightly more hardware looking) snippet:

 

wire  mux_select = s00_axis_tvalid & (~full);

wire write = (mux_select==1)? 1 : 0 ; wire wr_ptr_next = (mux_select==1)? wr_ptr_reg + 1 : wr_ptr_reg; wire wr_ptr_gray_next = (mux_select==1)? wr_ptr_next^(wr_ptr_next>>1) : wr_ptr_gray_next;

 

 

Observer roader
Observer
661 Views
Registered: ‎10-14-2015

Re: Understanding how blocking and non blocking statements work in this AXI4 interface

Jump to solution

Hi,

 

That makes sense. Thanks a lot.

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