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taichi730
Observer
Observer
1,770 Views
Registered: ‎07-02-2019

Unexpected "illegal context for assignment pattern" error

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Hi,

I'm trying to synthesis a design including user-defined struct type imported from an interface port like the sample code below.

interface foo_types;
  typedef struct packed {
    logic foo;
  } foo_struct;
endinterface

module sub (
  foo_types     types,
  input   logic i_clk,
  input   logic i_rst_n,
  input   logic i_a,
  output  logic o_b
);
  typedef types.foo_struct  foo_struct;
  //typedef struct packed {
  //  logic foo;
  //} foo_struct;

  foo_struct  foo;
  always_ff @(posedge i_clk, negedge i_rst_n) begin
    if (!i_rst_n) foo <= '0;
    else          foo <= '{ foo: i_a };
  end

  always_comb begin
    o_b = foo.foo;
  end
endmodule

module top (
  input   logic i_clk,
  input   logic i_rst_n,
  input   logic i_a,
  output  logic o_b
);
  foo_types types();
  sub u_sub (types, i_clk, i_rst_n, i_a, o_b);
endmodule

Abobe code is legal SV code but I got following error message when I tried to synthesis the code.

[Synth 8-2119] illegal context for assignment pattern ["/home/ishitani/workspace/test/illegal_assignment/illegal_assignment.sv":22]

This code is leagal so I think this error is caused by Vivado's bug.

I found two workarounds for this error.

  • Define foo_struct type within module sub instead of imporintg the struct type from interface port
//typedef types.foo_struct  foo_struct;
typedef struct packed {
  logic foo;
} foo_struct;
  • Assign the value to the 'foo' member directly instead of using struct litera
always_ff @(posedge i_clk, negedge i_rst_n) begin
  if (!i_rst_n) foo     <= '0;
  else          foo.foo <= i_a;
end

I've confirmed that the avove two workaround wok well.

Regards,
Taichi Ishitani

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1 Solution

Accepted Solutions
pulim
Xilinx Employee
Xilinx Employee
1,713 Views
Registered: ‎02-16-2014

Hi @taichi730 

 

Thanks for reporting this issue.

I filed CR to fix this issue in future releases of vivado. 

 

Thanks,

Manusha

View solution in original post

5 Replies
chandu_sathi
Adventurer
Adventurer
1,722 Views
Registered: ‎05-08-2019

You also can assign all operators at once without assigning to each operator.

 

foo_struct  foo;
  always_ff @(posedge i_clk, negedge i_rst_n) begin
    if (!i_rst_n) foo <= '0;
    else          foo <= '{ i_a };
  end

 

pulim
Xilinx Employee
Xilinx Employee
1,714 Views
Registered: ‎02-16-2014

Hi @taichi730 

 

Thanks for reporting this issue.

I filed CR to fix this issue in future releases of vivado. 

 

Thanks,

Manusha

View solution in original post

taichi730
Observer
Observer
1,680 Views
Registered: ‎07-02-2019

Hi @pulim ,

Thank you for filing CR.
How can I track status of this CR?

Regards,
Taichi Ishitani

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taichi730
Observer
Observer
1,675 Views
Registered: ‎07-02-2019

Hi @pulim ,

I think that following issue which I found is also casued by Vivado's bug.
https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Synth-8-448-named-port-connection-error-on/m-p/992566 
Could you please look into this issue too?

Regards,
Taichi Ishitani

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taichi730
Observer
Observer
1,612 Views
Registered: ‎07-02-2019

Hi @chandu_sathi ,

Thank you for your adivice.
Your workaround is legal SystemVerilog code but the same error occurs.

Regards,
Taichi Ishitani