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1,155 Views
Registered: ‎02-26-2019

Unsupported Clock Statement error

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I'm making a divide by 5 clk like this:

if (rising_edge(clk) or falling_edge(clk)) then
    count:= count+1;
     if count=4 then
     sma_clk<= NOT sma_clk;
     count:=0;
     end if;
   end if;

it passes syntax check but the synthesis gives me ": unsupported Clock statement. error.

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Highlighted
1,082 Views
Registered: ‎01-22-2015

ritchiew@golighthouse.com 

Welcome to the Xilinx Forum !

Your VHDL code snippet give us lots to talk about…

1) As steven notes, the Xilinx tools will complain about your “if (rising_edge(clk) or falling_edge(clk)) then”.  In a VHDL process, you can use either “rising_edge(clk)” or “falling_edge(clk))” but not both (see VHDL Sequential Logic in Xilinx document UG901).

2) You call “sma_clk” a clock, but your VHDL indicates that it is a signal (officially called a toggle).  Toggles are very useful, but they should not be used directly as clocks.  For example, you should not elsewhere use “if (rising_edge(sma_clk)) then”.

3) If you want “sma_clk” to be a clock then you should generate it using a FPGA Clock Management Tile (CMT), which is probably how you are generating “clk”.   That is, we usually bring a single base clock into the FPGA and immediately route it to a CMT, which can then be configured to create other clocks (typically up to 6ea) needed by the design.  For many of the Xilinx FPGAs, configuring a CMT is described by document PG065).

4) If you want “sma_clk” to be a toggle, then we usually create the toggle, sma_tog, as shown in process, P1, and use the toggle as shown in process, P2:

P1: process(clk)
    constant COUNT_MAX : integer := 4;
    variable count : integer range 0 to COUNT_MAX := 0;
    begin
        if rising_edge(clk) then
            if(count = COUNT_MAX) then
                sma_tog <= '1';
                count := 0;
            else
                sma_tog <= '0';
                count := count + 1;              
            end if;             
        end if;
    end process P1;	
	
P2: process(clk)
    begin
        if rising_edge(clk) then
            --here, things done at rate of clk
            if(sma_tog = '1') then
                --here, things done at rate of sma_tog
            end if;  
        end if;
    end process P2;	

Cheers,
Mark

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6 Replies
Highlighted
Contributor
Contributor
1,148 Views
Registered: ‎10-25-2018

Does your target support dual-edge flip-flops? Also, similar to tri-state buffers, dual-edge flip-flops oftentimes need to be in the top level module / entity.

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Highlighted
1,145 Views
Registered: ‎02-26-2019

AH! Thanks for the hint. I'll check that out. Thanks

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Highlighted
1,083 Views
Registered: ‎01-22-2015

ritchiew@golighthouse.com 

Welcome to the Xilinx Forum !

Your VHDL code snippet give us lots to talk about…

1) As steven notes, the Xilinx tools will complain about your “if (rising_edge(clk) or falling_edge(clk)) then”.  In a VHDL process, you can use either “rising_edge(clk)” or “falling_edge(clk))” but not both (see VHDL Sequential Logic in Xilinx document UG901).

2) You call “sma_clk” a clock, but your VHDL indicates that it is a signal (officially called a toggle).  Toggles are very useful, but they should not be used directly as clocks.  For example, you should not elsewhere use “if (rising_edge(sma_clk)) then”.

3) If you want “sma_clk” to be a clock then you should generate it using a FPGA Clock Management Tile (CMT), which is probably how you are generating “clk”.   That is, we usually bring a single base clock into the FPGA and immediately route it to a CMT, which can then be configured to create other clocks (typically up to 6ea) needed by the design.  For many of the Xilinx FPGAs, configuring a CMT is described by document PG065).

4) If you want “sma_clk” to be a toggle, then we usually create the toggle, sma_tog, as shown in process, P1, and use the toggle as shown in process, P2:

P1: process(clk)
    constant COUNT_MAX : integer := 4;
    variable count : integer range 0 to COUNT_MAX := 0;
    begin
        if rising_edge(clk) then
            if(count = COUNT_MAX) then
                sma_tog <= '1';
                count := 0;
            else
                sma_tog <= '0';
                count := count + 1;              
            end if;             
        end if;
    end process P1;	
	
P2: process(clk)
    begin
        if rising_edge(clk) then
            --here, things done at rate of clk
            if(sma_tog = '1') then
                --here, things done at rate of sma_tog
            end if;  
        end if;
    end process P2;	

Cheers,
Mark

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Tags (1)
Highlighted
1,059 Views
Registered: ‎02-26-2019

Thank you so much for your explaination. I'm new to the VHDL world, so this will be a big help to me, thanks!

Ritchie

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Highlighted
1,032 Views
Registered: ‎02-26-2019

Just as a follow up, I used the Spartan 3E DCM primative and setting up a divide by 5 clock was easy as pie. The clock was connected to an external sma connector and used to drive an A/D converter demo board. 

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Xilinx Employee
Xilinx Employee
1,017 Views
Registered: ‎05-14-2008

ritchiew@golighthouse.com Could you help to mark solution with the answer that helped you solve the issue?

-vivian

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