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Visitor
Visitor
13,976 Views
Registered: ‎03-03-2015

Unsupported unconstrained arrays within records?!

Hi,

 

I'm using Vivado 2014.4 (I also tried 2014.3) on linux.  I have the following in a package file:

 

  type complex is record
    re : signed ;
    im : signed ;
  end record;

 

In my file.vhd I have:

 

signal signal_A    :  complex( re(15 downto 0), im(15 downto 0));

 

The error I get:

 

ERROR: [Synth 8-1018] re is not a type [file location]

ERROR: [Synth 8-1018] im is not a type [file location]

 

I don't understand considering this looks to be legal vhdl-2008.  I even added this into my build script:

 

set_property vhdl_version vhdl_2008 [current_fileset]

 

Are unconstrained arrays within records unsupported and why?

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Moderator
Moderator
13,964 Views
Registered: ‎01-16-2013

Hi,

Try re-naming "re" & "im".
Also specify the length of array in record type.

Example:
type complex is
record
re_value : signed(15 downto 0);
im_value : signed (15 downto 0);
end record;

signal signal_A : complex ( re_value(15 downto 0), im_value(15 downto 0));

--Syed

 

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Observer
Observer
13,951 Views
Registered: ‎04-04-2013

@sydez: The point of an unconstrained record is that you DON'T specify the length of an array at the record declaration, only when you use it.

 

Most good design tools can also infer the record length if you use it as an input port for example.

 

So the quesiton is does Vivado support this? (I know synplify does)

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Visitor
Visitor
13,941 Views
Registered: ‎03-03-2015

I can confirm that changing the name doesn't work.  I completely agree with the above point that the reason I'm doing this is to avoid needing a different record for each data length when I have more than a few.  This should be supported and is in many other tools.

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Visitor
Visitor
11,392 Views
Registered: ‎12-16-2015

This is now working on Vivado 2015.4

The only thing is you need to enable VHDL-2008 for the specific file that you want to compile with VHDL-2008. I used the following TCL commands in the script I use to create a project:

# This option makes VHDL-2008 accessible
set_param project.enableVHDL2008 1
# Enable VHDL-2008 on the project
set_property enable_vhdl_2008 1 [current_project]
# Set all the VHDL files to VHDL-2008
set_property file_type {VHDL 2008} [get_files *.vhd]

If you only want VHDL-2008 support on a specific file then use:
set_property file_type {VHDL 2008} [get_files MyFile.vhd]

Hope this helps
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Adventurer
Adventurer
7,572 Views
Registered: ‎01-27-2008

I am not getting the same results as Jloyola (and, yes type = VHDL 2008).

 

Tried this in a design, however I get the following error:
[Synth 8-318] illegal unconstrained array declaration 'ctl_mstr_wadr_ch_u' ["pcie_subsystem.vhd":115]


This is the record used in this declaration:
  type axi_wadr_chan_rcrd_tu is record
    awid    : std_logic_vector;  -- needed as slave
    awaddr  : std_logic_vector;
    awlen   : std_logic_vector;   -- Should be x"00" on slave
    awsize  : std_logic_vector;   -- "010" on slv
    awburst : std_logic_vector;
    awvalid : std_logic;
  end record axi_wadr_chan_rcrd_tu;


I defined the axi channels using this construct:
  -- axi lite master that uses unconstrained records
  signal ctl_mstr_wadr_ch_u : axi_wadr_chan_rcrd_tu;
  signal ctl_mstr_wsig_ch_u : axi_write_sigs_chan_rcrd_tu;
  signal ctl_mstr_wdat_ch_u : axi_wdata_chan_rcrd_tu;
  signal ctl_mstr_radr_ch_u : axi_radr_chan_rcrd_tu;
  signal ctl_mstr_rdat_ch_u : axi_rdata_chan_rcrd_tu;

 

As I sometimes use AXI 32/64 bus, it is convenient to have unconstrained arrays in records.

This is using 2015.4 on Linux.
This issue is currently out as as Xilinx SR - I'll update when they do.

 

Jerry

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Visitor
Visitor
2,010 Views
Registered: ‎10-16-2013

Back to the future, I am experiencing exactly the same problem in Vivado 2018.3.

Never solved? This is very troublesome because I am using 3rd party code that uses unbound arrays within a record.

Which is perfectly valid according to VHDL 2008.

However, if I need to "fix" 3rd party code, its warranty will be void!

Please fix this (again)!

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Teacher
Teacher
2,001 Views
Registered: ‎07-09-2009

Its rumoured Xilinx does not use VHDL internally

and so the possibility of it being fixed is low, and if it is , the possibility of it re occurring in another build is high.

I am well ***** as its the language most of the companies I see in Europe use, but hay , I just have to write System Verilog as if its VHDL, ..

Unfortunately, after I move on, some *** modifies the code, using old Verilog stuff, and all the checking goes out the window,,
but fortunately , I then get the contract to sort out the mess..

roll on the great SystemVerilog , Im making good money of it.

rant over
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Scholar
Scholar
1,968 Views
Registered: ‎08-01-2012

@stuifmeel 

What errors are you seeing? I am using unconstrained arrays inside records without issue in 2018.2. 2008 support in 2018.2 is pretty useable (for synthesis, forget the simulator) and gets even better in 2019.1.

NOTE: Objects of an unconstrained type must not have null length arrays - this is a very old vivado bug that never seems to get fixed. Workaround is to make it length 1 and leave it unconnected. Note this was reported in 2012, and still broken:

https://www.xilinx.com/support/answers/53503.html

I suspect it's because it does some kind of conversion underneath to Verilog or some other common format, which does not support null length arrays.

Can you post any code that exhibits the problem?

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Visitor
Visitor
1,922 Views
Registered: ‎10-16-2013

As requested a code snippet that illustrates the problem, I have included line numbers where it would be handy:

Messages:
[Synth 8-692] width mismatch in association of record element 'id'; element has 1 bits, expression has 6 bits ["C:/source/addr_access_ctrl.vhd":57]
[Synth 8-692] width mismatch in association of record element 'user'; element has 1 bits, expression has 4 bits ["C:/source/addr_access_ctrl.vhd":67]
[Synth 8-318] illegal unconstrained array declaration 'AXI4_MASTER_MOSI_DEFAULTS' ["C:/source/addr_access_ctrl.vhd":55]

Declaration:

package axi4_pkg is

-- The naming of the AXI4 record type are following the naming of the AXI4
-- specification.
--
-- AW : Write Address Channel
-- W : Write Data Channel
-- B : Write Response Channel
-- AR : Read Address Channel
-- R : Read Data Channel

-- Generic Address Channel
type t_axi4_ax_ch_mosi is
record
id : unsigned;
addr : unsigned(31 downto 0);
len : unsigned( 7 downto 0);
size : unsigned( 2 downto 0);
burst : unsigned( 1 downto 0);
lock : std_logic;
cache : unsigned( 3 downto 0);
prot : unsigned( 2 downto 0);
qos : unsigned( 3 downto 0);
region : unsigned( 3 downto 0);
user : unsigned;
valid : std_logic;
end record;

...

Instantiation:

55 constant AXI4_MASTER_MOSI_DEFAULTS : t_axi4_ax_ch_mosi :=
56 (
57 id => (axi4_master_ax_mosi.id'range => '0'),
58 addr => (others => '0'),
59 len => (others => '0'),
60 size => AXI4_BURST_SIZE_1,
61 burst => AXI4_BURST_INCR,
62 lock => AXI4_NORMAL_ACCESS,
63 cache => AXI4_W_DEVICE_NON_BUF,
64 prot => (others => '0'),
65 qos => (others => '0'),
66 region=> (others => '0'),
67 user => (axi4_master_ax_mosi.user'range => '0'),
68 valid => '0'
69 );

 

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Explorer
Explorer
1,914 Views
Registered: ‎06-25-2014

I could be wrong, but is this where you add RichardHeads answer record information into your code so that:

id : unsigned;
becomes:
id : unsigned(-1 downto 0);

and this tricks the tools into treating it as unconstrained

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Scholar
Scholar
1,902 Views
Registered: ‎08-01-2012

@andrewlan  No. That is an unconstrained record type that works just fine.

@stuifmeelThis does appear to be a bug, but only with constant declarations (because this would illegal for signals or variables until VHDL 2019 gets any support). I would usually declare all sizes in the type declaration (or just create a constrained subtype) hence Ive never hit it.

You can work around it by putting the sizes in the subtype declaration for the constant:

constant AXI4_MASTER_MOSI_DEFAULTS : t_axi4_ax_ch_mosiid( id(axi4_master_ax_mosi.id'range),
                                                          user(axi4_master_ax_mosi.user'range ) )

:=
(
   id     => (others => '0')
   addr   => (others => '0'),
   len    => (others => '0'),
   size   => AXI4_BURST_SIZE_1,
   burst  => AXI4_BURST_INCR,
   lock   => AXI4_NORMAL_ACCESS,
   cache  => AXI4_W_DEVICE_NON_BUF,
   prot   => (others => '0'),
   qos    => (others => '0'),
   region => (others => '0'),
   user   => (others => '0'),
   valid  => '0'
);
Highlighted
Visitor
Visitor
1,873 Views
Registered: ‎10-16-2013

Thanks, that really solved the issue!

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Xilinx Employee
Xilinx Employee
1,849 Views
Registered: ‎02-16-2014

Hi @stuifmeel 

Able to reproduce this width mismatch error with below code:

type test_rec is record
ele:unsigned;
end record;
constant temp: test_rec := (ele => "1111");

I reported this issue to get it fixed.

When I use the part of code that you shared I see a different error like this:

ERROR: [Synth 8-211] could not evaluate expression: unresolved type without a constraining context 
ERROR: [Synth 8-211] could not evaluate expression: aggregate choice expression

Can you confirm are you seeing same error as Synth 8-211?

 

Thanks,

Manusha

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Visitor
Visitor
1,840 Views
Registered: ‎10-16-2013

Hi Manusha,

As you can see from my post the error I got was different.

I don't recognize the error you see...

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Visitor
Visitor
591 Views
Registered: ‎04-29-2019

I have also a problem with unconstrained records and tried this sollution here: https://www.xilinx.com/support/answers/71725.html

Is this answer record working for anybody??

When I try this decleration in my packege:

type test_rec is
record
clk : STD_LOGIC;
rst : STD_LOGIC;
vector: STD_LOGIC_VECTOR;
end record test_rec; 

I get this error message in elaborate.log file

ERROR: [VRFC 10-1310] record element cannot be unconstrained

I'm using Vivado 2019.2

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Scholar
Scholar
582 Views
Registered: ‎08-01-2012

@hofo 

Did you set the file type to VHDL 2008? Your code is illegal in previous versions and will give that error.

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Visitor
Visitor
567 Views
Registered: ‎04-29-2019

@richardheadthank you for your response.

I changed the filetype to VHDL 2008. Now I receive the following error message:

ERROR: [XSIM 43-4187] File "D:/project/package.vhd" Line 42: The "Vhdl 2008 Record with Unconstrained Element" is not supported yet for simulation.

Maybe the problem is that synthesis is possible but not simulation?

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Scholar
Scholar
552 Views
Registered: ‎08-01-2012

Yes. The simulator is far behind the synthesis for 2008 support.

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Moderator
Moderator
478 Views
Registered: ‎07-21-2014

@hofo 

Since you are seeing the issue with the simulator, you can use below board to post your queries on simulation:
https://forums.xilinx.com/t5/Simulation-and-Verification/bd-p/SIMANDVERIBD

Thanks
Anusheel 

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