Hi there, I'm running some stuff on a Virtex 5 part but would like to use the new and heavily updated Virtex 6 verilog parser. Is there anyway to do this? I don't see why the new parser should only run on V6 and not V5/4 etc.
More specifically, I would like support for 'variable bit-part selects' on the LHS of equations for V5 parts. IE:signal1[variable+:8] = signal2;
Please go ahead and create a case with Xilinx Technical Support.
They should be able to help you to atleast with a workaorund to be used in V-5 parser.