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Registered: ‎02-23-2019

User supplied safe state not applied

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We are using Vivado 2019.1 and a xcku060-ffva1517-2-e device.  I trying to configure a FSM with a fsm_safe property, but it doesn't seem to be accepted, so I'm looking for some help as to why.

The state machine VHDL code is the following:

type t_AW_STATE is (IDLE_st, VLD_st, WAIT_NO_VLD_st);
signal aw_curr_state, aw_next_state : t_AW_STATE;

-- Write Address State Control
p_aw_curr_state : process(S_AXILITE_CLK)
begin
if rising_edge(S_AXILITE_CLK) then
if (S_AXILITE_RST_N='0') then
aw_curr_state <= IDLE_st;
else
aw_curr_state <= aw_next_state;
end if;
end if;
end process p_aw_curr_state;

p_aw_state_transition : process(aw_curr_state, axilite_awvalid)
begin
case aw_curr_state is
when IDLE_st =>
if (axilite_awvalid='1') then
aw_next_state <= VLD_st;
else
aw_next_state <= aw_curr_state;
end if;

when VLD_st =>
aw_next_state <= WAIT_NO_VLD_st;

when WAIT_NO_VLD_st =>
if (axilite_awvalid='0') then
aw_next_state <= IDLE_st;
else
aw_next_state <= aw_curr_state;
end if;

when others => aw_next_state <= IDLE_st;
end case;
end process p_aw_state_transition;

The fsm_safe property is being applied in a XDC file as follows, and does appear to be recognized: set_property fsm_safe_state auto_safe_state [get_cells {<path>/aw_curr_state_reg[*]}]

However, the synthesizer log reports the following:

INFO: [Synth 8-4559] User supplied safe state for register 'aw_curr_state_reg' not applied because reachable default state already exists
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle_st | 0001 | 00
vld_st | 0010 | 01
wait_no_vld_st | 0100 | 10
iSTATE | 1000 | 11
*
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'aw_curr_state_reg' using encoding 'one-hot' in module 'fpga_maintain_ifc'

Any help would be much appreciated.

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Xilinx Employee
Xilinx Employee
331 Views
Registered: ‎06-14-2018

Re: User supplied safe state not applied

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Hi cpawlowski@planetiq.com ,

Thanks @drjohnsmith for asking testcase.

Here vivado identiifies state sequence is such that next state logic(combinational) takes care of any illegal state. This means with current implementation if state machine goes in illegal state, it will fall back to IDLE_st (default state). No extra logic is required to achieve same.

If you need auto-correction logic, try commenting (others => '<default stae>') in case statement.

Thanks,

Ajay  

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4 Replies
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Teacher
Teacher
390 Views
Registered: ‎07-09-2009

Re: User supplied safe state not applied

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how about posting the whole code as an attachment please
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Highlighted
380 Views
Registered: ‎02-23-2019

Re: User supplied safe state not applied

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See the attached project archive.  As mentioned above, several FSMs (including aw_curr_state_regf) do not infer safe FSM... but several do.

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Xilinx Employee
Xilinx Employee
332 Views
Registered: ‎06-14-2018

Re: User supplied safe state not applied

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Hi cpawlowski@planetiq.com ,

Thanks @drjohnsmith for asking testcase.

Here vivado identiifies state sequence is such that next state logic(combinational) takes care of any illegal state. This means with current implementation if state machine goes in illegal state, it will fall back to IDLE_st (default state). No extra logic is required to achieve same.

If you need auto-correction logic, try commenting (others => '<default stae>') in case statement.

Thanks,

Ajay  

View solution in original post

Highlighted
Teacher
Teacher
312 Views
Registered: ‎07-09-2009

Re: User supplied safe state not applied

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just to close the loop for others , refer to this

https://www.xilinx.com/support/answers/60799.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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