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rkmichaelswa
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Registered: ‎11-01-2016

Using VHDL "protected type" and shared variable to infer dual port block ram

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After reading some of the other posts on infer-ing block ram using VHDL shared variables I realized that to make it work in VHDL-2002/2008 I need to have it in a  protected type body definition. I also saw one post that said to get VHDL-2003 features (ie: protected types)  in 14.7 XST with a Virtex 5 I needed to include "use_new _parser yes" in the XST config file. This did not work. (see error message below)

 

Does XST in ISE 14.7 support "protected types" and if so any suggestions on how to make it work?

 

Are protected types supported in Vivado and will that work to infer block rams?

 

Thanks,

Robert

 

 [debug] -- stdout: ERROR:HDLCompiler:806 - "xnc2_generic.vhd" Line 66: Syntax error near "protected".
 [debug] -- stdout: ERROR:HDLCompiler:806 - "xnc2_generic.vhd" Line 69: Syntax error near "end".
 [debug] -- stdout: ERROR:HDLCompiler:806 - "xnc2_generic.vhd" Line 71: Syntax error near "protected".
 [debug] -- stdout: ERROR:HDLCompiler:806 - "xnc2_generic.vhd" Line 84: Syntax error near "end".
 [debug] -- stdout: ERROR:HDLCompiler:750 - "xnc2_generic.vhd" Line 103: Record name prefix type ram_type_protected is not a record type
 [debug] -- stdout: ERROR:HDLCompiler:750 - "xnc2_generic.vhd" Line 114: Record name prefix type ram_type_protected is not a record type
 [debug] -- stdout: ERROR:HDLCompiler:750 - "xnc2_generic.vhd" Line 130: Record name prefix type ram_type_protected is not a record type
 [debug] -- stdout: ERROR:HDLCompiler:750 - "xnc2_generic.vhd" Line 144: Record name prefix type ram_type_protected is not a record type
 [debug] -- stdout: ERROR:HDLCompiler:925 - "xnc2_generic.vhd" Line 71: Missing full type definition for ram_type_protected

LINE 66
  type ram_type_protected is protected
    procedure  setR(addr : in std_logic_vector(addr_width-1 downto 0); data : in  std_logic_vector(data_width-1 downto 0));
    impure function readR(addr : in std_logic_vector(addr_width-1 downto 0)) return std_logic_vector;
  end protected ram_type_protected;
 
  type ram_type_protected is protected body
      type ram_type is array ((2**addr_width)-1 downto 0) of std_logic_vector (data_width-1 downto 0);
      variable RAM : ram_type := (others => (others => '0'));
      attribute ram_style        : string;
      attribute ram_style of RAM : variable is imp_style;
                                       
      procedure  setR(addr : in std_logic_vector(addr_width-1 downto 0); data : in std_logic_vector(data_width-1 downto 0)) IS
        begin
          RAM(to_integer(unsigned(addr))) := data;
      end procedure setR;
 
      impure function readR(addr : in std_logic_vector(addr_width-1 downto 0)) return std_logic_vector IS
        variable temp : std_logic_vector(data_width-1 downto 0);
        begin
          temp := RAM(to_integer(unsigned(addr)));
          return(temp);
       end function readR;
 
  end protected body;

 shared variable R : ram_type_protected;

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rkmichaelswa
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Registered: ‎11-01-2016

Balkrishan and Rohit,

 

Many thanks for your replies clarifying what XST supports. I'll steer clear of protected types for now.

 

Robert

 

View solution in original post

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balkris
Xilinx Employee
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Registered: ‎08-01-2008
check this AR
https://www.xilinx.com/support/answers/33123.html

Vivado Synthesis supports a synthesizable subset of the VHDL 2008 standard.

For details on setting up VHDL-2008 in Vivado for both Project & Non-Project flow, and to learn about the supported VHDL-2008 subset, please refer to the 2015.3 (UG901) Synthesis User guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-vivado-synthesis.pdf

Thanks and Regards
Balkrishan
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thakurr
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Registered: ‎09-15-2016

Hi @rkmichaelswa

 

Protected type is still not supported in Vivado synthesis. We have already filed a CR on this saying tool should show clear message saying protected type not supported. It is to be fixed in Vivado version 2017.1.

 

Regards

Rohit

 

 

Regards
Rohit
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rkmichaelswa
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Registered: ‎11-01-2016

Balkrishan and Rohit,

 

Many thanks for your replies clarifying what XST supports. I'll steer clear of protected types for now.

 

Robert

 

View solution in original post

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aklemd
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Registered: ‎07-10-2017

Then what is the recommended way for now  to have synthesizable single clock dual-port block-ram in VHDL-2008 standard if using shared variables (unprotected or protected) is not possible?

 

Using a signal results in "XXX..X" when simulating.

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richardhead
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Registered: ‎08-01-2012

@aklemd

 

The only time you need a shared variable is to infer write first behaviour. If you don't need write first, then a signal is fine. If you have xxxx then you probably have multiple drivers, which is a problem. A shared variable would mask this problem, so you need to fix your code.

 

If you really must have write first behaviour, then you will need to write '93 VHDL.

aklemd
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Registered: ‎07-10-2017

I forgot to mention I need a 'write first' bram. That's unfortunate as I use unconstrained arrays in an entity port and really would have liked not to implement this in VHDL 93.

 

Any idea when write first, dual port bram in VHLD2008 will be possible to synthesize in future Vivado releases?

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richardhead
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What kind of unconstrained arrays? unconstrained 1d arrays on ports have been allowed since '93 which are sized on connection.  But for 2d you are a little stuck.

 

How about conversion functions that convert to a 1d arrays, and then extract the individual busses from the large 1d array. It takes some of the pain out:

 

generic (
  BW  : integer : 8 -- width of each bus
)
port (
  ip : in std_logic_vector;   -- this can be unconstrained
....

type 2d_t is array(0 to ip'length/BW -1) of std_logic_vector(BW-1 downto 0);
signal internal_bus : 2d_t;

function bus_remap(s : std_logic_vector) return 2d_t is
  variable b : 2d_t;
begin
  for i in 2d_t'range loop
    b(i)   <= ip((i+1*BW-1 downto i*BW);
  end loop;
  return b;
end function;

....


assert( ip'length rem BW = 0) report "BW does not match multiple bus sizes" severity failure;


internal_bus <= bus_remap(ip);
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geoffbarnes
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Registered: ‎09-07-2011

This thread has some info as well.

 

https://forums.xilinx.com/t5/Synthesis/Can-VHDL-shared-variables-be-synthesized/td-p/838978

 

For single clock, you should be able to use ONE process for read/write logic.   Can use either a process variable or a signal, which is easily supported from VHDL-87 thru VHDL-2008..

 

For dual clock, apparently  Vivado will let you use 2 clocks in ONE process as well.   This may or may not be an officially supported by the the tool.

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uwbtest
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Registered: ‎04-13-2019

I was really trying to get your code, and was disturbed by this line:

It's missing a bracket after i+1 before *. It wouldn't compile

b(i)   <= ip((i+1*BW-1 downto i*BW);

Should be:

b(i)   <= ip((i+1)*BW-1 downto i*BW);

 

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