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rikusleroux
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Registered: ‎05-21-2009

Using a Verilog header file in VHDL

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Hi guys and girls,

 

I just need some advice on how to approach this.

 

I've downloaded a Xilinx reference design for an application note (XAPP879). This reference design was written in Verilog and uses a header file (.h) full of Verilog functions. As such, one of the higher level modules contains `include "pll_drp_func.h".

 

Now, I am busy rewriting this reference design in VHDL, since we want to use some of the aspects in a larger design. Unfortunately, it is my understanding that VHDL does not fascilitate the inclusion of header files in a manner similar to Verilog. How would you recommend I include the header file? I see some forums suggest modifying the header file into a package, but I am not sure if the Verilog package will be compatible with the higher level VHDL modules. Not only that, but the header file is also quite complex and contains numerous functions. I am not really that familiar with verilog and packages, and don't want to waste time trying to port it if its not necessary.

 

Edit: Sorry, forgot to mention that we are using ISE 13.4

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muravin
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Registered: ‎11-21-2013

You need to convert the header file into VHDL package, then add 'use' clause on the library / package.

 

Verilog functions and calculations done with `define($name) can be replaced by VHDL functions.

 

BR

Vlad

Vladislav Muravin

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muravin
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Registered: ‎11-21-2013

You need to convert the header file into VHDL package, then add 'use' clause on the library / package.

 

Verilog functions and calculations done with `define($name) can be replaced by VHDL functions.

 

BR

Vlad

Vladislav Muravin

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rikusleroux
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Registered: ‎05-21-2009
Hi Vlad,

Thank you very much for the reply. So, if I understand your reply correctly, there is no way to use the header file as is in VHDL?
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muravin
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No you cannot. If I may ask, why do you need to recode in VHDL? Verilog is much better on this front. Also, why can't you use a mixed-signal project?

 

Vladislav Muravin
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rikusleroux
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Hi again Vlad,

 

My initial thought was that it would be simpler to analyse issues in the project if all the sources are in the same HDL. However, I've since come to the realisation that by trying to port the Verilog to VHDL could cause potential other issues. So for now I am rather going for a mixed signal project.

 

Could you please elaborate on why Verilog is better on this front? I don't have much experience with Verilog and fail to see why it would be better in this instance.

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muravin
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Well, Verilog vs VHDL has been subject of many discussions and I certainly don't want to start one here :o)

Bottom line is that you should be comfortable with what you are using.
Vladislav Muravin
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rikusleroux
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Registered: ‎05-21-2009
Haha! Ok, point taken :-)

Thanks for all your help. I will continue with a mixed signal project.
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