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Using of loop statements and delays inside the states in fsm

Hi All,

         I'm trying to write a vhdl code for generating the multiple frequencies in single channel.. That is 242.72khz with 20 cycles and 23.6khz with 1 cycle and 243.90khz with 6 cycles and then 23.4 khz with 386 cycles.. all in single output.

just  i tried with one frequency here and got some issues with delays in codes.. Here i attached my code and please help me with developing the code..I mentioned each states with different no.of cycles here..But what i need is ( for ex: if state S0=242.72khz with 20 cycles in one state and a delay in between two states and next with 23.6khz with one cycle and delay and next state and so on..)

In between the codes i worked some loops and delays which i comment them, please dont mind that..

 

 

Thanks in advance...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM_Example is
	port ( clk, reset, en : in std_logic;
			 output : inout std_logic);
end FSM_Example;

architecture Behavioral of FSM_Example is
Type state_type is ( S0, S1, S2, S3 );
signal cur_state, next_state : state_type;
signal count : integer range 0 to 5000;
signal i : integer range 0 to 400;
signal cnt : integer range 0 to 400;
begin
state_memory : process (clk, reset)
begin
if ( reset='1' ) then
cur_state <= S0;
elsif (clk='1' and clk'event) then
if (count = 4240-1) then
count <=0;
cur_state <= next_state;
else
count <= count +1;
end if;
end if;
end process state_memory;

process(count)
begin
if(count < 1480) then
output <= '1';
else 
output <= '0';
end if;
end process count;


process ( en, cur_state )
--variable i : integer range 0 to 400;
begin
case cur_state is

when S0 =>
loop0:for i in 0 to 6 loop
exit loop0 when i=7;
cnt(i+1) <= cnt(i)+1;
if (en='1' and en'event) then
elsif ( i < 6 ) then
next_state <= S1;
else
next_state <= S0;
--wait for 2 us;
end if;
end loop;

--if (next_state = S1) then
--output <= '1';
--elsif (next_state = S0) then
--output <='0';
--end if;
--wait for 1 us;

when S1 =>
loop1:for i in 0 to 1 loop
exit loop1 when i=2;
i <= i+1;
if (en='1' and en'event) then
elsif ( i < 1 ) then
next_state <= S2;
else
next_state <= S1;
--wait for 2 us;
end if;
end loop;


--if (next_state = S2) then
--output <= '1';
--elsif (next_state = S1) then
--output <='0';
--end if;
--wait for 2 us;

when S2 =>
loop2:for i in 0 to 20 loop
exit loop2 when i=21;
i <= i+1;
if (en='1' and en'event) then
elsif ( i < 20 ) then
next_state <= S3;
else
next_state <= S2;
--wait for 2 us;
end if;
end loop;


--if (next_state = S3) then
--output <= '1';
--elsif (next_state = S2) then
--output <='0';
--end if;
--wait for 3 us;

when S3 =>
loop3:for i in 0 to 386 loop
exit loop3 when i=387;
i <= i+1;
if (en='1' and en'event) then
elsif ( i < 386 ) then
next_state <= S0;
else
next_state <= S3;
--wait for 2 us;
end if;
end loop;


--when S4 =>
--for i in 0 to 6 loop
--if (en='1' and en'event) then
--cur_state <= next_state;
--else 
--next_state <= S0;
--end if;
--end loop;

--if (next_state = S0) then
--output <= '1';
--elsif (next_state = S3) then
--output <='0';
--end if;
--wait for 5 us;

--case cur_state is 
--when S0 => transport S3 after 1 us;
--     S1 => transport S0 after 2 us;
--     S2 => transport S1 after 3 us;
--	  S3 => transport S2 after 4 us;
--when others => null;
--end case;

end case;




end process;
end Behavioral;
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Re: Using of loop statements and delays inside the states in fsm

Hi,

 

I have made a small example for you. It does not exactly do what you want, you have to analyze it for your application.

 

However, please pay attention to several things:

1. Try to make your code cleaner

2. Understand the structure. If you use en'event you are telling the tool that en is a clock. It is not recommended to define multiple clocks if not needed

3. Wait cannot be synthesized

4. It is preferable to use constants and not hard-coded numbers in the code

 

entity top is
  Port ( 
    clk       : in STD_LOGIC;
    reset     : in STD_LOGIC;
    data_out  : out STD_LOGIC
  );
end top;

architecture Behavioral of top is
  constant PERIOD1  : natural := 242720;
  constant PERIOD2  : natural := 23600;
  constant PERIOD3  : natural := 57400;
  constant CNT1     : natural := SYS_FREQ / (2 * PERIOD1);
  constant CNT2     : natural := SYS_FREQ / (2 * PERIOD2);
  constant CNT3     : natural := SYS_FREQ / (2 * PERIOD3);
  constant NCYCLES1 : natural := 3;
  constant NCYCLES2 : natural := 1;
  constant NCYCLES3 : natural := 2;
    
  signal   freq_cnt : unsigned(15 downto 0);
  signal   cyc_cnt  : unsigned(15 downto 0);
  signal   edge     : std_logic;
  
  type sm_type is (idle, cyc1, cyc2, cyc3);
  signal   state    : sm_type;  
begin

  seq_pr : process(clk)
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        state    <= idle;
        edge <= '0';
      else  
        edge <= '0';

        case(state) is
          when idle =>
            freq_cnt <= to_unsigned(CNT1, 16); 
            cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
            state    <= cyc1;  
          when cyc1 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT2, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES2-1, 16);          
                state    <= cyc2;
              else   
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT1, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc2 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT3, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES3-1, 16);          
                state    <= cyc3;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT2, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc3 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT1, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
                state    <= cyc1;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT3, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when others =>
            state <= idle;
        end case;
      end if;
    end if;  
  end process seq_pr;           

  out_pr : process(clk)
    variable toggle : std_logic;
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        toggle := '0';
      else  
        if (edge = '1') then
          toggle := not toggle;
        end if;
      end if;
      
      data_out <= toggle;    
    end if;
  end process out_pr;

end Behavioral;

And this is a simulation. Notice that I have used less frequencies, and a different number of cycles. But once you understand the code it is easy to make what you want, adding some definitions and additional states.

 

multifreq.PNG

 

In the simulation you can see three freq. at the output, each one appearing for the number of cycles defined.

 

Hope this helps.

Cheers!

Avi

 

Avi Chami MSc
FPGA Site
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Re: Using of loop statements and delays inside the states in fsm

thank you @a_chami..

Now i got some ideas about my code..

But when i tried to synthesize it, i got lot of errors as 'natural' is not declared and "unsigned is not declared.. which library is exactly working for this errors..I tried it with "numeric_std.all;" and "std_logic_arith.all;"

So what is the solution for this?

 

Thank you.

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Re: Using of loop statements and delays inside the states in fsm

Hi All,

These are all the errors i get when i tried to synthesize it..

 

"sys_freq" cannot be used in this expression.
ERROR:HDLCompiler:16 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 35: <sys_freq> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
ERROR:HDLCompiler:16 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 36: <period1> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
ERROR:HDLCompiler:16 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 37: <period2> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
ERROR:HDLCompiler:16 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 38: <period3> cannot be used within its own interface list. Please verify that you don't use this object for the definition of other interface components.
ERROR:HDLCompiler:854 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 34: Unit <fsm_4> ignored due to previous errors.
Parsing architecture <Behavioral> of entity <fsm_4>.
ERROR:HDLCompiler:374 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 52: Entity <fsm_4> is not yet compiled.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 63: <unsigned> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 64: <unsigned> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 65: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 76: <edge> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 78: <edge> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 74: <reset> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 73: <rising_edge> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 71: <clk> is not declared.
ERROR:HDLCompiler:69 - "D:\Vijay\HTIC\Work\FSM_4\FSM_4.vhd" Line 87: <freq_cnt> is not declared.
Sorry, too many errors..

 

 

 

How can i resolve it.. 

Thanks in advance..

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Re: Using of loop statements and delays inside the states in fsm

Hi,

 

For the libraries, try this:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

 

SYS_REQ is your reference frequency in Hz. Sorry that I forgot to mention it.

Let's say that your reference clock is 100MHz, then you should add:

 

constant SYS_FREQ : natural := 100_000_000; -- system clock frequency in Hz

 

(In my test I added that constant to an external package, which makes it simpler to write the testbench. But you can add this definition to your FSM module).

 

Cheers!

Avi

Avi Chami MSc
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Re: Using of loop statements and delays inside the states in fsm

Hi All,

Now i cleared all those errors.. But simulation is not working..

I got an error as" The simulation has terminated in an unexpected manner.."

 

Any ideas to recover the simulation..

 

Thanks in advance...

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Re: Using of loop statements and delays inside the states in fsm

I think that the best is that you post your simulation code here...

Avi Chami MSc
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Re: Using of loop statements and delays inside the states in fsm

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--use WORK.my_package.all;
entity FSM_4 is
--	Generic ( SYS_FREQ : integer := 50_000_000);
--				 PERIOD1  : natural := 242720;
--				 PERIOD2  : natural := 23600;
--				 PERIOD3  : natural := 23400;
--				 CNT1     : natural := SYS_FREQ / (2 * PERIOD1);
--				 CNT2     : natural := SYS_FREQ / (2 * PERIOD2);
--				 CNT3     : natural := SYS_FREQ / (2 * PERIOD3);
--				 NCYCLES1 : natural := 3;
--				 NCYCLES2 : natural := 1;
--				 NCYCLES3 : natural := 2);
	Port ( 
    clk       : in STD_LOGIC;
    reset     : in STD_LOGIC;
    data_out  : out STD_LOGIC
  );
end FSM_4;

architecture Behavioral of FSM_4 is
constant SYS_FREQ : natural :=100_000_000;
constant PERIOD1  : natural := 242720;
  constant PERIOD2  : natural := 23600;
  constant PERIOD3  : natural := 23400;
  constant CNT1     : natural := SYS_FREQ / (2 * PERIOD1);
  constant CNT2     : natural := SYS_FREQ / (2 * PERIOD2);
  constant CNT3     : natural := SYS_FREQ / (2 * PERIOD3);
  constant NCYCLES1 : natural := 3;
  constant NCYCLES2 : natural := 1;
  constant NCYCLES3 : natural := 2; 
  signal   freq_cnt : unsigned (15 downto 0);
  signal   cyc_cnt  : unsigned(15 downto 0);
  signal   edge     : std_logic:='0';
  
  type sm_type is (idle, cyc1, cyc2, cyc3);
  signal   state    : sm_type;  
begin

seq_pr1 : process(clk) 
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        state    <= idle;
        edge <= '0';
      else  
        edge <= '0';
		 end if;
		 end if;
end process seq_pr1;

seq_pr2 : process ( edge, freq_cnt, cyc_cnt)
begin
      case(state) is
          when idle =>
            freq_cnt <= to_unsigned(CNT1, 16); 
            cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
            state    <= cyc1;  
          when cyc1 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT2, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES2-1, 16);          
                state    <= cyc2;
              else   
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT1, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc2 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT3, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES3-1, 16);          
                state    <= cyc3;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT2, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc3 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT1, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
                state    <= cyc1;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT3, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when others =>
            state <= idle;
        end case;
  --    end if;
--    end if;  
  end process seq_pr2;           

  out_pr : process(clk)
    variable toggle : std_logic;
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        toggle := '0';
      else  
        if (edge = '1') then
          toggle := not toggle;
        end if;
      end if;
      
      data_out <= toggle;    
    end if;
  end process out_pr;



end Behavioral;

Now code will look like this... Is everything right?

ISIM is getting crashed..

Error: "The simulation has terminated in an unexpected manner"..

what to do now?

 

Thanks..

 

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Re: Using of loop statements and delays inside the states in fsm

Hi,

 

I don't use ISIM, I use Vivado. 

If you haven't done simulations before I advice you that you start with very simple projects, a single FF, a shift register, and adder, a counter, write test benches for them and then you can debug more complex designs like the one we are talking about.

 

Do not try to debug using only force commands or the like. Learn how to properly set a test bench. I am sure there are tutorials for ISIM if you haven't done that before.

 

Cheers!

Avi

Avi Chami MSc
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Re: Using of loop statements and delays inside the states in fsm

Using fsm is only new to me..This is the first time i've been trying to do like multiple frequencies with fsm..

Can you please post the code you wrote?..May be i can get some more clear ideas.. 

 

Thanks @a_chami

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Re: Using of loop statements and delays inside the states in fsm

Hi,

 

Here is the package I used

library ieee;
  use ieee.std_logic_1164.all;
	use ieee.numeric_std.ALL;
    
package top_pkg is
    constant SYS_FREQ : natural := 100_000_000;		-- system clock frequency in Hz
end top_pkg;

 

And here my test bench (it is really, really simple). Look, it includes the top_pkg file where the SYS_FREQ constant is defined.

Then it just runs the clock for some time.

 

 

library ieee;
    use ieee.std_logic_1164.all;
	use ieee.numeric_std.ALL;
  	use work.top_pkg.all;
    
entity tb_top is
end entity;

architecture test of tb_top is

    constant PERIOD  : time   := 1_000_000_000/SYS_FREQ * 1ns;

    signal clk       : std_logic := '0';
    signal reset     : std_logic := '1';
    signal endSim	   : boolean   := false;

    component top is
    port (
        reset     : in  std_logic;                       
        clk       : in  std_logic;               
        data_out  : out std_logic               
    );
    end component;
    

begin
  clk     <= not clk after PERIOD/2;
  reset   <= '0' after  PERIOD*10;
  endSim  <= true after  PERIOD*100000;

	-- End the simulation
	process 
	begin
		if (endSim) then
			assert false 
				report "End of simulation." 
				severity failure; 
		end if;
		wait until (clk = '1');
	end process;	

    DUT : top
    port map (
        clk      => clk,
        reset    => reset,
        data_out => open
    );

end architecture;

 

 

Avi Chami MSc
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Re: Using of loop statements and delays inside the states in fsm

Hi @a_chami 

The sequence and cycles of output is okay, but the frequencies is not as given in "period" and "cnt" values..

can you please elaborate the calculations for 242.72khz?

I can't get the desired frequency by giving period and cnt value as in the code..

 

Thanks.

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Re: Using of loop statements and delays inside the states in fsm

Hi @vjkaran,

 

In my simulation the period of the 242KHz signal is 4.12us which is close enough, within the resolution achievable with a 100MHz clock. What is your measurement?

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Re: Using of loop statements and delays inside the states in fsm

1. 242.72 khz- 4.12 us period and on-time-1.6 us.---cyc_1

2. 23.36 khz- 42.8 us period and on-time-26.60 us.---cyc_2

3. 243.90 khz- 4.3 us period and on-time-1.7 us.---cyc_3

4. 23.4khz- 42.6 us period and on-time-1.6 us.---cyc_4

 

these are requirements..i've attached my simulation results.

 

How did you calculate the timings?..

my calc--  period=sys_freq/required freq..

duty cycles are given as per requirement..

 

 

 

cyc_1.png
cyc_2.png
cyc_3.png
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Re: Using of loop statements and delays inside the states in fsm

Hi,

 

The code as I wrote it uses symmetric waveforms as you didn't specify earlier the 'on' time.

 

The period = SYS_FREQ / 2 * REQ_FREQ;  -> notice you forgot the '2' factor (hint: also review the code and check how the waveforms are generated by means of the 'edge' signal).

 

But if you need specific 'on' times and not symmetric waves you will have to change my algorithm. If I were you I would use two counters, one for the 'on' time for each frequency and one for the frequency itself.

 

I hope that you will be able to make those changes by yourself.

 

Cheers,

Avi

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Re: Using of loop statements and delays inside the states in fsm

Hi @a_chami  now my code looks like this..what i need to change? i told my requirements on previous message..

 

Here i attached my code..

 

Thanks..

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--use WORK.my_package.all;
entity FSM_5 is

	Port ( 
    clk       : in STD_LOGIC;
    reset     : in STD_LOGIC;
    data_out  : out STD_LOGIC
  );
end FSM_5;

architecture Behavioral of FSM_5 is
constant SYS_FREQ : natural :=100_000_000;---- sys_freq @ 100 mhz
constant PERIOD1  : natural := 412; ---period for 242.72khz
  constant PERIOD2  : natural := 4280; ----period for 23.36khz
  constant PERIOD3  : natural := 410;-----period for 243.90khz
  constant PERIOD4 : natural :=4273; -----period for 23.4khz
  constant CNT1     : natural := 160; --- on-time 1.6 us for 242.72 khz
  constant CNT2     : natural := 2660; ---on-time 26.6 us for 23.36khz
  constant CNT3     : natural := 162; ---on-time 1.6 us for 243.90 khz
  constant CNT4     : natural := 160;----on-time 1.6 us for 23.4 khz
  constant NCYCLES1 : natural := 5;---no.of cycles @ 242.72khz
  constant NCYCLES2 : natural := 3;----no.of cycles @ 23.6 khz
  constant NCYCLES3 : natural := 2; --- no.of cycles @ 243.90khz
  constant NCYCLES4 : natural := 1; --- no.of cycles @ 23.4 khz
  signal   freq_cnt : unsigned (15 downto 0);
  signal   cyc_cnt  : unsigned(15 downto 0);
  signal   edge     : std_logic:='0';
  
  type sm_type is (idle, cyc1, cyc2, cyc3, cyc4);
  signal   state    : sm_type;  
begin

seq_pr : process(clk) 
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        state    <= idle;
        edge <= '0';
      else  
        edge <= '0';
		 end if;
		 end if;
--end process seq_pr1;

--seq_pr2 : process ( edge, freq_cnt, cyc_cnt)
--begin
      case(state) is
          when idle =>
            freq_cnt <= to_unsigned(CNT1, 16); 
            cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
            state    <= cyc1;  
          when cyc1 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT2, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES2-1, 16);          
                state    <= cyc2;
              else   
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT1, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc2 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT3, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES3-1, 16);          
                state    <= cyc3;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT2, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
          when cyc3 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT4, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES4-1, 16);          
                state    <= cyc4;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT3, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
				 when cyc4 =>
            if (freq_cnt = 0) then  
              edge     <= '1';
              if (cyc_cnt = 0) then
                freq_cnt <= to_unsigned(CNT1, 16);          
                cyc_cnt  <= to_unsigned(2 * NCYCLES1-1, 16);          
                state    <= cyc1;
              else                 
                cyc_cnt  <= cyc_cnt - 1;              
                freq_cnt <= to_unsigned(CNT4, 16);          
              end if;
            else     
              freq_cnt <= freq_cnt - 1;
            end if;  
				
          when others =>
            state <= idle;
        end case;
  --    end if;
--    end if;  
end process seq_pr;           

  out_pr : process(clk)
    variable toggle : std_logic;
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        toggle := '0';
      else  
        if (edge = '1') then
          toggle := not toggle;
        end if;
      end if;
      
      data_out <= toggle;    
    end if;
  end process out_pr;



end Behavioral;
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Contributor
Contributor
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Registered: ‎03-14-2017

Re: Using of loop statements and delays inside the states in fsm

Like the following code..

state_memory : process (clk, reset)
begin
if ( reset='1' ) then
cur_state <= S0;
elsif (clk='1' and clk'event) then
if (count = 412-1) then  ---412 is period value for 242.72khz
count <=0;
cur_state <= next_state;
else
count <= count +1;
end if;
end if;
end process state_memory;

process(count)
begin
if(count < 160) then  ---- 160 is duty of 242.72khz
output <= '1';
else 
output <= '0';
end if;
end process count;

Here how can i include all four frequencies?.. and how can i get it working with states?

That is the doubt...

 

Thanks.. 

@a_chami

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