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Adventurer
Adventurer
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Registered: ‎01-19-2012

Utilization of logic resources for different length counters.

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Hello,

I have synthesized two simple synchronous counters, both with reset and enable. One version is a 16-bit counter, while the other is an 8-bit. When I synthesize the 16-bit counter my logic resource usage is 1 LUT and 16 FFs, and when I synthesize the 8-bit counter my logic resource usage is 6 LUTs and 8 FFs. Digging into the schematics I find that for the 16-bit counter, the single LUT is used to implement the boolean equation for the LSB (B0 = not(B0 previous)), and then four CARRY4 blocks are used. In the 8-bit version there are no CARRY4s, and there are 6 LUTs. These LUTs implement the exact boolean equations needed for each of the 8 bits. So, a couple questions.

1) How many CARRY4 primitives are there in a particular FPGA? Is there one per slice, except maybe for the top slice in each column?

2) Is there a way to disable the packing of such logic into carry primitives, or enable it, if one type of resource (LUT vs CARRY4) is more valuable to me than another? I checked the UG901 Vivado Synthesis User Guide but didn't see much. 

3) How does Vivado choose which type of resource is more valuable? This is synthesis only so no timing information has been input yet.

I tried to attach exported vivado schematic files for each implementation but the forum automatically removed them due to the following.

The attachment's schematic16.sch content type (application/octet-stream) does not match its file extension and has been removed.

I have attached screenshots of relevant portions to try and illustrate.

counter16.PNG
counter8.PNG
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Xilinx Employee
Xilinx Employee
392 Views
Registered: ‎07-21-2014

Hi @kwiatlab 

 

1) How many CARRY4 primitives are there in a particular FPGA? Is there one per slice, except maybe for the top slice in each column?
There is one carry4 primitive per slice. you can check CLB resources user guide for more information on carry4 (7 series CLB)
https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

2)Is there a way to disable the packing of such logic into carry primitives, or enable it, if one type of resource (LUT vs CARRY4) is more valuable to me than another? I checked the UG901 Vivado Synthesis User Guide but didn't see much.
There is a directive that you can use to set higher adder threshold and use fewer carry chains.
-directive FewerCarryChains you can specify this option in GUI -> synthesis settings -> More options

Or if this does not work, you can use block_synth property on the sub-module instance.
eg.
set_property BLOCK_SYNTH.ADDER_THRESHOLD {17} [get_cells inst]

where "inst" is instance of counter. However Block synth flow will only work on the instance. you can see more info under Block-Level flow in UG901.

3)How does Vivado choose which type of resource is more valuable? This is synthesis only so no timing information has been input yet.
With respect to optimized timing there seems to be a default threshold of 11, after which tool will implement adder using CARRY4 when adder drives register. However you can change this value with block synth constrain as mentioned above.

 

-Shreyas

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1 Reply
Xilinx Employee
Xilinx Employee
393 Views
Registered: ‎07-21-2014

Hi @kwiatlab 

 

1) How many CARRY4 primitives are there in a particular FPGA? Is there one per slice, except maybe for the top slice in each column?
There is one carry4 primitive per slice. you can check CLB resources user guide for more information on carry4 (7 series CLB)
https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

2)Is there a way to disable the packing of such logic into carry primitives, or enable it, if one type of resource (LUT vs CARRY4) is more valuable to me than another? I checked the UG901 Vivado Synthesis User Guide but didn't see much.
There is a directive that you can use to set higher adder threshold and use fewer carry chains.
-directive FewerCarryChains you can specify this option in GUI -> synthesis settings -> More options

Or if this does not work, you can use block_synth property on the sub-module instance.
eg.
set_property BLOCK_SYNTH.ADDER_THRESHOLD {17} [get_cells inst]

where "inst" is instance of counter. However Block synth flow will only work on the instance. you can see more info under Block-Level flow in UG901.

3)How does Vivado choose which type of resource is more valuable? This is synthesis only so no timing information has been input yet.
With respect to optimized timing there seems to be a default threshold of 11, after which tool will implement adder using CARRY4 when adder drives register. However you can change this value with block synth constrain as mentioned above.

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post