02-25-2010 11:04 AM
When synthesizing a parameterized verilog design targeted for a Virtex-6 part with XST 11.4, the resolved parameters and localparams are not listed in the synthesis report. Is there a trick, i.e. magic environment variable, to get them listed?
02-25-2010 01:44 PM
Ok, I jumped the gun a bit on that. Formal parameters are listed inline, by module in the HDL Elaboration section.
But no sign of any localparams. Any ideas?
02-26-2010 07:50 AM
02-26-2010 12:15 PM
I beg to differ, localparams are not just used for simple constants. They have the same
utility as parameters while having the advantage of not being directly modifiable by errant
Parameterized code can be difficult to debug if bad values are hidden. To illustrate
the point, the fallowing module fragment contain both in-line parameter and localparam
statements, added for illustration, as well as a formal parameters list in the header.
Note that the localparam statements contain a parsing bug which results in the three
values not being equal:
parameter T_SELECT = "V5", // device select: "S3A, "S6", "V4", "V5" or "V6" only
V4_MODE = "V4_CODE", // V4 mode: "V4_FIFO" or "V4_CODE", na in other modes
FREE_LIM = 32, // free space limit for almost_full
D_WIDTH = 36, // default bus size
Dtop = D_WIDTH -1 // top bit #
input clk, // system clock
sinit, // synch init
wr_en, // fifo write
rd_en, // fifo read
input [Dtop:0] din, // n-bit input data
output full, // fifo full flag
a_full, // almost full flag
empty, // fifo empty flag
output [Dtop:0] dout // n-bit output data
parameter INLINE_PARAM = FREE_LIM + 1;
localparam INLINE_LOCAL1 = FREE_LIM - T_SELECT == "V5" ? 2 : 1,
INLINE_LOCAL2 = FREE_LIM - (T_SELECT == "V5") ? 2 : 1,
INLINE_LOCAL3 = FREE_LIM - (T_SELECT == "V5" ? 2 : 1);
Targeting a Virtex-5 part, the synthesis report reveals that the first two
localparam results are wrong and only the third has the correct value:
Analyzing hierarchy for module <sym_fifo_1kxN> in library <work> with parameters.
D_WIDTH = "00000000000000000000000000010010"
Dtop = "00000000000000000000000000010001"
FREE_LIM = "00000000000000000000000000100000"
INLINE_LOCAL1 = "00000000000000000000000000000001"
INLINE_LOCAL2 = "00000000000000000000000000000010"
INLINE_LOCAL3 = "00000000000000000000000000011110"
INLINE_PARAM = "00000000000000000000000000100001"
T_SELECT = "V5"
V4_MODE = "V4_CODE"
While retargeting synthesis to Virtex-6, all in-line values are hidden:
Synthesizing Unit <sym_fifo_1kxN>.
Related source file is "d:/hdl/xxx/sym_fifo.v".
T_SELECT = "V6"
V4_MODE = "V4_CODE"
FREE_LIM = 32
D_WIDTH = 18
Dtop = 17
Interesting too is the fact that the compiler has changed the in-line parameter into
a local because of the presence of a formal list:
WARNING:HDLCompiler:693 - "D:\HDL\xxx\sym_fifo.v" Line 37: Parameter declaration
becomes local in sym_fifo_1kxN with formal parameter declaration list
To my knowledge, mixed formal and in-line parameter use is not prohibited by the
Verilog-2001 spec. so I guess this must be a compiler "feature".
02-26-2010 01:13 PM
Sorry, my mistake. Now I see where you're coming from. This looks a deficiency in the new parser. I will follow up with you via PM.
03-26-2012 06:39 AM
I am also encountering this issue where the value of an inline parameter is not being displayed in the synthesis report when the relevant module also has formal parameters being passed to it from an upper module. When I remove the formal parameters, the synthesis report properly displays all inline parameter values. However, I need to be able to pass the formal parameters so I cannot remove them from my module.
I understand this is due to a problem with the Virtex-6 parser, but how can I resolve this issue so that the value gets displayed and I can debug that the correct value of the inline parameter is being used in the module?