05-09-2019 02:27 AM
When can we expect support for VHDL 2008 Context feature?
context my_context is library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library some_lib; use some_lib.some_package.all; end context my_context; library my_lib; context my_lib.my_context;
08-02-2019 12:46 AM - edited 08-02-2019 01:41 AM
Hi @richardhead ,
I tried to create a simple test case, using context in VHDL-2008 in Vivado 2019.1 and there it is not supported. I also tested the same test case on upcoming Vivado release internal builds and there it is getting synthesized successfully and also the context color shade is in pink which repersents that it has been added in upcoming release.So i guess itwill be available in the upcoming release build.
Attached the test case RTL.
08-16-2020 05:14 PM
I have been using this context definition in my designs (Vivado 2019.1) without issue:
------------- Top of a package file I have --------
context vhdl_std_libs is
end context vhdl_std_libs;
------ Library definition on the top of all of my HDL files -------
08-16-2020 11:14 PM - edited 08-16-2020 11:14 PM
What error did you encountered when using VHDL context?
Please start a new post for your question, with details about the problem.
09-17-2020 08:12 AM - edited 09-17-2020 08:21 AM
@viviany, I tested context support again in 2020.1 and found it to work. I do not recall the specifics of the problems encountered previously, but I was mistaken to assert that 2020.1 does not support contexts.
However, the Vivado editor does not appear to be aware of the ieee_std_context. It synthesizes fine, but the editor displays "Error: suffix 'ieee_std_context' in the context reference does not denote a context declaration". Is this a bug in the editor or am I doing something wrong?
09-18-2020 12:26 PM
I rediscovered the problem with context support in 2020.1. If the top-level VHDL file is not of type VHDL-2008, then contexts may not be used in other files in the design even if they are of type VHDL-2008. "Just set the top-level VHDL file to type VHDL-2008, then", right? The problem then is that the design cannot be added as a module to IP Integrator because IP Integrator does not support modules with a top-level file of type VHDL-2008.
What that means then, is that contexts cannot be used in a design if it is to be instantiated as a module in IP Integrator. This is quite unfortunate. I have attached a test case that demonstrates this. If you synthesize as-is, it will fail and report "ERROR: [Synth 8-2713] suffix test_ctx in the context reference does not denote a context declaration". If you change test.vhd to type VHDL-2008, synthesis then succeeds. Please verify my findings and report this to the development team. Thank you.
05-04-2021 06:33 AM
So it appears this has actually been supported since Vivado 2019.2. Shame noone at Xilinx updated UG901 to reflect the fact (no mention in 2020.2 version)
@viviany any chance of a CR to sort out the documentation?
06-11-2021 12:51 AM