05-13-2020 04:03 AM - edited 05-14-2020 01:48 AM
I have an UltraScale project in Vivado 2019.2 where I use VHDL modules in the block diagram.
So here are my observations:
Is that keyword theory true, or what could be the issue? If yes, could you please add checks for such “keyword abuse”(?) errors, so that other users in the future immediately see that such modules have invalid names, instead of getting pointed to seemingly correct referencing statements?
And why can I set the testbench to VHDL-2008, but not a regular source file? Both are referencing the `Parameter` module and use pretty much the same variables of that module in the same way.
05-13-2020 02:38 PM
Parameter is a reserved word in VHDL 2008, because it is was a PSL reserved word.
You dont say what the error is - was it something about expecting some other stuff?
05-14-2020 03:23 AM - edited 05-14-2020 03:25 AM
I don’t recall the exact error message, but I was referenced to `xvhdl.log` where there was just an unspecific complaint like “an error in line 6” (which is the line of the `use work.Parameter.all;` statement) – not a specific error message at all (which is the problem here, because it took me quite a long time to realize the usage of the registered keyword). Furthermore, there were of course errors for all missing variables, which I have defined in that package.
Would be nice if both the GUI and the `xvhdl.log` would tell me about an invalid package name instead.
05-21-2020 02:42 PM
You may also want to be careful with the use of "use work.Parameter.all".
work is nat actually a library in VHDL but a reference to the current working library.
Early on everybody just compiled everything into work so the tools all allow this.
It can however cause compilation problems.
I prefer to compile everything into properly named libraries and reference them accordingly.