cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
246 Views
Registered: ‎11-20-2018

VHDL-2008 module name restrictions

I have an UltraScale project in Vivado 2019.2 where I use VHDL modules in the block diagram.

  • I created a module `Parameter.vhdl` containing just a package `Parameter`.
  • I have another module `MotorControl.vhdl`, which references that `Parameter` package.
  • Due to the non-VHDL-2008 top module synthesis restriction, I have that aforementioned module sitting below a wrapper `MotorControlW`.
  • Then, there’s also my testbench `MotorControl_TB`, which references the `Parameter` and the `MotorControlW` modules.

So here are my observations:

  • When all files are declared as VHDL (i.e. old non-2008), both Simulation and Synthesis work fine.
  • I can declare the Testbench as VHDL-2008 without issues.
  • When I then declare either the `Parameter` or the `MotorControlW` module (or both) as VHDL-2008, I always get errors complaining about my `use work.Parameters.all` statement. Additionally, the “Sources” ⇒ “Libraries” widget of Vivado now shows me the `Parameter` module as unreferenced. Setting `IS_GLOBAL_INCLUDE` avoids the referencing error, but still complains about not known variables.
  • Finally, I guessed that `parameter` might be a reserved keyword and renamed that module – since then everything (Simulation & Syntheses) seems to work as VHDL-2008.

Is that keyword theory true, or what could be the issue? If yes, could you please add checks for such “keyword abuse”(?) errors, so that other users in the future immediately see that such modules have invalid names, instead of getting pointed to seemingly correct referencing statements?

And why can I set the testbench to VHDL-2008, but not a regular source file? Both are referencing the `Parameter` module and use pretty much the same variables of that module in the same way.

0 Kudos
3 Replies
Highlighted
Scholar
Scholar
204 Views
Registered: ‎08-01-2012

Re: VHDL-2008 module name restrictions

Parameter is a reserved word in VHDL 2008, because it is was a PSL reserved word.

You dont say what the error is - was it something about expecting some other stuff?

0 Kudos
Highlighted
164 Views
Registered: ‎11-20-2018

Re: VHDL-2008 module name restrictions

I don’t recall the exact error message, but I was referenced to `xvhdl.log` where there was just an unspecific complaint like “an error in line 6” (which is the line of the `use work.Parameter.all;` statement) – not a specific error message at all (which is the problem here, because it took me quite a long time to realize the usage of the registered keyword). Furthermore, there were of course errors for all missing variables, which I have defined in that package.

 

Would be nice if both the GUI and the `xvhdl.log` would tell me about an invalid package name instead.

0 Kudos
Highlighted
Adventurer
Adventurer
111 Views
Registered: ‎05-09-2018

Re: VHDL-2008 module name restrictions

You may also want to be careful with the use of "use work.Parameter.all".

work is nat actually a library in VHDL but a reference to the current working library.

Early on everybody just compiled everything into work so the tools all allow this.

It can however cause compilation problems.

I prefer to compile everything into properly named libraries and reference them accordingly.