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Adventurer
Adventurer
15,058 Views
Registered: ‎12-09-2010

VHDL-2008 support in Vivado

Hello,

 

will Vivado support synthesis of designs which use VHDL-2008 language syntax?

 

 

Best regards

Martin 

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24 Replies
Historian
Historian
15,042 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@stmartin81 wrote:

Hello,

 

will Vivado support synthesis of designs which use VHDL-2008 language syntax?

 

 

Best regards

Martin 


Wouldn't that be swell!

 

But don't hold your breath!

----------------------------Yes, I do this for a living.
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Adventurer
Adventurer
15,032 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado

Unfortunately I would be very surprised if Xilinx would offer full VHDL-2008 support. ISE for example still (and I guess will never) support the "process(all)" statement.

 

Does anyone know what the recommended language for programming Xilinx FPGAs is? I had a quick look at Verilog but it isn't a strongly typed language which I really dislike. Would SystemVerilog (I gues as it builds on Verilog it also isn't a strongly typed language?) and C + HSL be a safe bet?

 

I came to appreciate the features of the VHDL language and the 2008 standard improvements are great. What are the advantages Verilog offers to VHDL? I've come across this site:  http://www.angelfire.com/in/rajesh52/verilogvhdl.html and after  skimming through the text there doesn't seem to be any reason for me to switch to Verilog as it doesn't seem to offer any advanced features to me.

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Teacher rcingham
Teacher
15,022 Views
Registered: ‎09-09-2010

Re: VHDL-2008 support in Vivado

> Does anyone know what the recommended language for programming Xilinx FPGAs is?

If you want strongly-typed, then VHDL-93 is what to go with. Read The Fine XST Manual (parser version depending on what family you are targetting) for details on the synthesizeable subset supported.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Historian
Historian
15,010 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@stmartin81 wrote:

Unfortunately I would be very surprised if Xilinx would offer full VHDL-2008 support. ISE for example still (and I guess will never) support the "process(all)" statement.

 

Does anyone know what the recommended language for programming Xilinx FPGAs is? I had a quick look at Verilog but it isn't a strongly typed language which I really dislike. Would SystemVerilog (I gues as it builds on Verilog it also isn't a strongly typed language?) and C + HSL be a safe bet?

 

I came to appreciate the features of the VHDL language and the 2008 standard improvements are great. What are the advantages Verilog offers to VHDL? 


First off: I'm a VHDL partisan, although I've used Verilog a lot in the past.

 

A lot of the VHDL'2002 stuff that applies to synthesis actually is supported. See the XST guide. I don't know what Vivado (what a stupid name) will support. I think the most interesting thing that needs to be supported is the fixed type.

 

Both languages are supported and recommended. Which you choose is entirely up to you. If you prefer strong types (as I do) then VHDL is the only choice. If you want to do DSP and math, then again, VHDL is the right choice. If you want your customers to find your bugs, then you should use Verilog.

 

I don't know about the state of "affordable" C-based FPGA design. And for what it's worth, I don't see the point.

----------------------------Yes, I do this for a living.
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Advisor eilert
Advisor
15,006 Views
Registered: ‎08-14-2007

Re: VHDL-2008 support in Vivado

Hi,

are you just yearning for the process (all) feature?

 

Sensitivity lists are ignored by synthesis tools and so it's no issue for XST. (For ISIM it may be one.)

Also, when you are doing synchronous design, your average process should almost always look like this:

 

process(clk)

 

So what's the gain?

Ok, you might save mentioning the async reset sometimes. but anyway, it just concernes the simulation tools.

 

 

What really would make a difference is the support of the new packages for float and std_numeric_unsigned.

And once they support these, implemeting the (all) into ISIM shouldn't be such a problem.

 

Actually I don't understand why the standards group at Acellera made this (all) statement at all?

If the simulators are mature enough to identify the used inputs by themselves, they could also ignore the sensitivity list.

So the general syntax would be like

 

[label:] process [(this_crap_is_optional_and_totally_useless_therefore_ignored)] is

 begin

 end [process [label]];

 

Any sensitivity list from old sources could then be ignored too, but still syntactically accepted without throwing an error.

Maybe that will be the improvement for VHDL-2015. :-)

 

 

Regards

  Eilert

 

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Adventurer
Adventurer
14,998 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado


@eilert wrote:

Hi,

are you just yearning for the process (all) feature?

 

Sensitivity lists are ignored by synthesis tools and so it's no issue for XST. (For ISIM it may be one.)

Also, when you are doing synchronous design, your average process should almost always look like this:

 

process(clk)

 

So what's the gain?

Ok, you might save mentioning the async reset sometimes. but anyway, it just concernes the simulation tools.

 

 

What really would make a difference is the support of the new packages for float and std_numeric_unsigned.

And once they support these, implemeting the (all) into ISIM shouldn't be such a problem.

 

Actually I don't understand why the standards group at Acellera made this (all) statement at all?

If the simulators are mature enough to identify the used inputs by themselves, they could also ignore the sensitivity list.

So the general syntax would be like

 

[label:] process [(this_crap_is_optional_and_totally_useless_therefore_ignored)] is

 begin

 end [process [label]];

 

Any sensitivity list from old sources could then be ignored too, but still syntactically accepted without throwing an error.

Maybe that will be the improvement for VHDL-2015. :-)

 

 

Regards

  Eilert

 


Hi Eilert,

 

synthesis will differ from simulation  when the sensitivity list is not correct. So yes I would like to see this feature implemented in XST. And perhaps it's not useful in most situations to make use of the sensitivity list but I could imagine that for simulation one could perhaps want the process to be only senstive to certain signals.

 

The question is not only about if VHDL-2008 will be supported but if VHDL in general will be supported as good as Verilog (I hope that Verilog is better supported than VHDL...). I've had occasions where the check syntax was ok but synthesis fails because obviously I've made a syntax error. I just don't see that Xilinx supports VHDL as a first class FPGA development language. I've had too many troubles already.

 

To be honest I haven't tried to use the following features which I used in another project where another FPGA technology was used. Can you tell me if these features are supported?:

   Matching case statements

  Signal expressions in port maps

  if and case generate statements

  PSL

  external names (useful during simulation)

Perhaps I've only tried to use the only feature which isn't supported?

 

Ah something else I had problems with:

... 

component parity_c is

  port(i_my_sig: in std_logic_vector(31 downto 0);

    parity: out std_logic);

end component  parity_c;

...

parity_inst: component parity_c

  port map (  i_my_sig => (others => '0'),

    parity => parity);

 

The "(others => '0')" statement isn't supported in this case. At least it's not supported for Spartan 3E according to the technical support. Why should it be device dependend if a VHDL statement is supported or not? 

 

Sorry if I sound a little bit frustrated that's because I am frustrated about these shortcomings.

 Regards

Martin 

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Advisor eilert
Advisor
14,994 Views
Registered: ‎08-14-2007

Re: VHDL-2008 support in Vivado

Hi Martin,

just checked what you said about the "others" statement in port lists. I did this for S6 and S3E.

In ISE14 this seems to be no problem anymore, neither for synthesis nor for Simulation with ISIM.

What version/tools were you using at that time?

 

You wrote "Synthesis will differ from simulation  when the sensitivity list is not correct."

But this statement is irritating, because it gives the impression that synthesis is doing something wrong.

Synthesis tools ignore the sensitivity list.

Therefore an incomplete sensitivity list leads to a wrong simulation result, nothing less, nothing more.

However, the tools are maturing and the "all" keyword gives a little convenience here, which is quite neglectible for clean synchronous designs. If you have lots of combinatorical processes, you might consider to rethink your coding style or use some checking tools. ( XST is so kind to give infos/wanrinigs about sensitivity list mismatches.)

 

About the features you requested, some are already in the standard and supported by ISE (e.g. if..generate, and some are only for simulation (PSL).

As for simulation I would use some other tool like Modelsim/Questasim, which already supports PSL or even Systemverilog.

Systemverilog has been announced to be supported by ISIM somewhen, but my personal opinion is that there is a VHDL-2008 compliant ISE before that. :-)

There are some more threads in the forum that help you rating the situation.

_______________

 

It seems like you fall for features rather than standards. :-)

What other FPGA tool (as you mentioned) did support the listed features?

Did these tools claim to support VHDL-2008?(e.g. matching case statements are not even supported by VHDL-2002)

Or was it just some vendor specific expansion? XST also knows some non-standard "tricks" like using file-IO in synthesis for ROM initialisation. You better not use it if you want your code to be usable with other tools.

 

So if you want to keep your code working on different tools, you better reduce your demands to the lowest common denominator.

(Or use a sophisticated 3rd party tool that can be used for all possible target technologies. But then you might lag behind using the latest FPGAs, while you are able to use the latest language features. Theres's always a tradeoff involved.)

 

But in any way, it's good that you raised your voice demanding a more actual language support for VHDL.

The more people showing interest, the sooner Xilinx will wake up and improve their tools.

 

Kind regards

  Eilert

 

 

Forum bumper sticker:

*********************************************************

**        KUDOS ME IF YOU WANT VHDL-2008 in ISE!       **

*********************************************************

 

 

 

 

 

 

Adventurer
Adventurer
14,989 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado

Hi Eilert,

 

I'm sorry about the example I've given above. Here is the answer from the technical support to my problem I had with the (others => '0') statement: "There is a know issue with the construct "(others => '0')" in the signal "a_din" and because this logic_vector use a Generic parameter to define its length I could not find any work around to be applied in HDL code."

The crucial part in my code seems to have been that I've used a generic to define the width of my port. It's been a few weeks already since I opened the webcase...

 

If a wrong simulation result gives me the behavior I want, I still get a wrong design when I synthesize the project. Normally I only code synchronous designs but even then I would have to remember to add the reset signal to my sensitivity list as Xilinx recommends to use asynchronous resets.

 

About the other vendor which supports VHDL-2008: I was working on an Altera project before and the Altera synthesis tool supports the constructs I've mentioned above. Most of my code is just generic VHDL code without any vendor specific extensions. I'm using Peter Ashenden's "The Designer's Guide To VHDL - Third Edition" and "VHDL-2008 Just The New Stuff" as reference books.

 

ModelSim in Version 10 also supports a lot of the VHDL-2008 features. But I do only have the ASE edition for Altera projects. And yes these tools claim to support VHDL-2008, at least some parts of the standard (luckily for me the parts which I had use for).

 

I thought the standard is called 2008 because it was passed in the year 2008. We now have 2012... 

 

PS: I've stumbled across another problem: I want to use configurations but XST's support for configurations is such limited that this feature is crippled for my usage...

 

Regards

Martin 

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Historian
Historian
14,983 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@stmartin81 wrote:

 

ModelSim in Version 10 also supports a lot of the VHDL-2008 features. But I do only have the ASE edition for Altera projects. And yes these tools claim to support VHDL-2008, at least some parts of the standard (luckily for me the parts which I had use for).

 

I thought the standard is called 2008 because it was passed in the year 2008. We now have 2012... 

 


 

Aldec's Active-HDL supports VHDL-2008, FWIW.

 

I suppose an option would be to pay $$$ for Synplify, but that's probably a budget-buster and despite various claims, I'm not sure that its quality of results is better than what XST offers.

 

I'm old enough to remember Synopsys FPGA Express never ever supporting VHDL'93, even though it was the synthesis tool Xilinx provided as late as what, 1998? And it was utter crap, which is probably why it was **bleep**canned. (And then Synopsys bought Synplicity.)

 

I can see the utility of the process(all) construct, but in at least my designs, I have so few combinatorial processes, especially a process with such a large sensitivity list as to make process(all) desireable, that it's not really an issue for me.  Reduction operators? PLEASE, bring it, already, for fsck's sake.

 

XST does support the VHDL'2002 feature that lets you do something like this (assume foo, bar and bletch are std_logic, not boolean):

 

    if foo and not bar then

        bletch <= '1';

    end if;

 

instead of

 

    if foo = '1' and bar = '0' then

         bletch <= '1';

    end if;

 

which is nice.

 


PS: I've stumbled across another problem: I want to use configurations but XST's support for configurations is such limited that this feature is crippled for my usage...


 

I know! I had this great idea of using a configuration to handle two different architectures for an entity, mainly because I wanted some code to support both Spartan 3 and Spartan 6. (Basically, the code needed to instantiate device-specific primitives and support for them.) It was simple enough to create the entity and the two architectures in a single source file, but XST wasn't too happy. The solution was to use a generic to control generate statements, which accomplishes basically the same thing, except it's not as elegant as the configuration version.

 

I suppose I should revisit it in 14.1. But now I'm trying to see if XST is able to synthesize something that uses a DSP48A1 slice where the opcodes are inferred from source. In other words, the actual operation of the DSP48A1 slice operation depends on the state of a couple of control bits. And so far, no dice.

----------------------------Yes, I do this for a living.
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Adventurer
Adventurer
11,103 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado

I totally forgot about Aledec's products. I've tested Riviera Pro and it made a good impression on me. Unfortunately I'm working only on smaller projects where the budget doesn't allow to buy a full-fledged simulator... 

@bassman59 wrote:

 

I know! I had this great idea of using a configuration to handle two different architectures for an entity, mainly because I wanted some code to support both Spartan 3 and Spartan 6. (Basically, the code needed to instantiate device-specific primitives and support for them.) It was simple enough to create the entity and the two architectures in a single source file, but XST wasn't too happy. The solution was to use a generic to control generate statements, which accomplishes basically the same thing, except it's not as elegant as the configuration version.


That's almost the same setup I have here. I'm working on a Spartan 3E project which will be ported to a Spartan 6 in a later revision. I've written two entities/architecture pairs and wanted to use the configuration file to decide which entity/architecture pair should be used in place of the component instantiation in my toplevel architecture. The idea was to include the Spartan 3E configuration file in the corresponding ISE project and to do the corresponding for the Spartan 6 project.

A colleague of mine also took the approach to use a generic to control a generate statement. It's a workaround which somewhat works, but which looks ugly to me compared to the configuration solution.

 

I've opened a webcase if I could achieve a configuration like behavior in some other way without having to touch my toplevel file, but after reading your post I can guess what the answer will be... 

 
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Advisor eilert
Advisor
11,102 Views
Registered: ‎08-14-2007

Re: VHDL-2008 support in Vivado

Hi everybody,

that "using std_logic like boolean" feature of VHDL-2002 is really nice.

Thanks bassman for mentioning it.

 

About the configuration stuff:

Sure, it would be nice to have this done by the language itself.

However, what still is missing is that you cant tell the tool which target device to use from the source code.

Or is there some vendor specific attribute which of I don't know?

 

So since it is necessary to set up a project for S3E implementation and another for S6 implentation (yes, I know, this can be done interactively "on the fly") why be bothered by  the missing configuration feature.

 

I would have set up a Tcl script for each implementation anyway and there I could do the necessary change to the used source names for the different implementations as well. (e.g. mem_s3e.vhd vs. mem_s6.vhd)

That's it, clean, reliable and compact.

 

Regards

  Eilert

 

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Historian
Historian
11,097 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@eilert wrote:

 

About the configuration stuff:

Sure, it would be nice to have this done by the language itself.

However, what still is missing is that you cant tell the tool which target device to use from the source code.

Or is there some vendor specific attribute which of I don't know?

 

So since it is necessary to set up a project for S3E implementation and another for S6 implentation (yes, I know, this can be done interactively "on the fly") why be bothered by  the missing configuration feature.

 


What should happen is that you have a top level entity which is specific to the design. (This is common and obvious.)

 

This top level instantiates lower-level entities.

 

Assume that one of your lower level entity has two architectures, one for S3 and the other for S6.

 

The instantiation of the lower-level in the upper level doesn't instantiate the entity; rather, it uses a configuration statement.

 

An example:

 

-- lower_level.vhdl:

entity lower_level is

    port ();

end entity lower_level;

 

architecture S6 of lower_level is

     ...

begin

    ....

end architecture S6;

 

architecture S3 of lower_level is

    ...

begin

    ...

end architecture S3;

 

Notice that two architectures are included in the source code for the entity. Both architectures are valid for that entity.

 

And the top level:

 

-- in top_level.vhdl:

entity upper_level is

    port ();

end entity upper_level;

 

architecture top_level_s3 of upper_level is

    ....

begin

 

    u1 : configuration work.lower_level(s3)

       port map ();

end architecture top_level_s3;

 

So, then, your top level chooses the architecture of the lower-level entity in the configuration instantiation.

 

A very common use of this is when you want to do a post-route backannotated timing simulation of your FPGA design using the same test bench used for functional simulation. The timing model from the tools has the same port list but a different architecture name. You write a configuration that exposes both architectures and in the simulation tool, you select the appropriate configuration as the top level, not the test bench entity itself.

 

Does this make sense? Most people find it crazy confusing.

----------------------------Yes, I do this for a living.
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Historian
Historian
11,095 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@eilert wrote:

 

So since it is necessary to set up a project for S3E implementation and another for S6 implentation (yes, I know, this can be done interactively "on the fly") why be bothered by  the missing configuration feature.


 

it is likely that in addition to the target device changing, there's other stuff in the design that is different. So your FPGA's top-level entity is different. The idea here is to create lower-level modules that can be used in any design, regardless of target architecture. The lower level entity exposes the same port list, and the different architectures take care of the differences in implementation.

 

 


I would have set up a Tcl script for each implementation anyway and there I could do the necessary change to the used source names for the different implementations as well. (e.g. mem_s3e.vhd vs. mem_s6.vhd)

That's it, clean, reliable and compact.

  


I kinda hate tcl scripting. And renaming things. The mem_s3e.vhd is a separate design entity from the mem_s6.vhd entity, and in a reasonable world, you would never have the s3e version source in the tree for an s6 design. So one entity called mem.vhd which does the right thing is preferable.

 

The obvious workaround is to have a source mem.vhd with a generic (a string such as "S3" or "S6" or perhap an integer which codes the family) passed through the port and generic maps, and that generic is used to control generate statements which basically turns on the code for the desired target. Again, the top level sets the appropriate generic. Something like:

 

entity lower_level is

    generic (TARGET : string := "S6");

    port ():

end entity lower_level;

 

architecture low of lower_level is

begin

 

    UseS6 : if TARGET = "S6" generate

        ...

    end generate UseS6;

 

    UseS3 : if TARGET = "S3" generate

        ...

    end generate UseS6;

end architecture low;

 

Which works well enough, I suppose.

 

----------------------------Yes, I do this for a living.
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Advisor eilert
Advisor
11,094 Views
Registered: ‎08-14-2007

Re: VHDL-2008 support in Vivado

Hi Bassman,

that's a nice summary about how configurations work and how to use them.

Everything you wrote is correct,  reasonable and desirable (according to the needed tool support of VHDL-2008).

There's only one assumtion you make that I would like to comment.

(I have to blame myself because I did the same in my little example, to keep it simple.)

 

You pointed out to have the Entity and Architectures in the same file. But why?

A very common alternative method is to have a separate file for each code segment (ent,arc,cfg,pkg).

Configurations select the architectures by their specific names, same could be done with file names.

So the entity for some function would always remain the same, and e.g. in some tcl script only the architecture names would be different according to the target technology.

 

Of course its a matter of personal taste which method is used by a designer (team) .

Many methods work and have their advantages and drawbacks.

Some people prefer having separate scripts for jumping between implementation and/or simulation flows.

Others have separate toplevel HDL files for that purpose.

In the end, if done properly, all methods should yield the same result.

 

Kind regards

  Eilert

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Teacher rcingham
Teacher
11,091 Views
Registered: ‎09-09-2010

Re: VHDL-2008 support in Vivado

> A very common alternative method is to have a separate file for each code segment (ent,arc,cfg,pkg).

I agree, but (in my experience) most company coding standards want the entity and architecture in the same file.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Adventurer
Adventurer
11,091 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado


@eilert wrote:

A very common alternative method is to have a separate file for each code segment (ent,arc,cfg,pkg).


I haven't thought about that solution. I think in my case it is the easiest and most elegant solution from the options I have available.

 

As this thread is about VHDL-2008 features, here's another VHDL-2008 feature which would be nice to have. I have a RAM module which uses a ram type for storing data:

SUBTYPE lookup_memory_t IS std_logic_vector((MEMORY_WORD_LENGTH_C - 1) DOWNTO 0);
TYPE lookup_memory_array_t IS ARRAY (0 TO ((2 * NUMBER_OF_LOOKUP_ELEMENTS_C) - 1)) OF lookup_memory_t;

The type is defined outside of the RAM module . Now I could use generics to define all the widths I need but with type generics I would be able to assign a pre initialized array to the RAM module:

entity my_ram is

  generic (type ram_t_g;

    initialization_vector _g:   ram_t );

  port

...

end entity my_ram;

 

architecture my_ram_arch of my_ram is

   memory :  ram_t_g := initialization_vector _g;

...

 

 I hope this example is not too esoteric...

 

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Advisor eilert
Advisor
11,088 Views
Registered: ‎08-14-2007

Re: VHDL-2008 support in Vivado

Hi Martin,

it's not that esoteric at all.

another example:

For complex systems ports are sometimes defined as records.

And in order to make this method even more flexible type generics can be helpful too.

 

There are many good improvements, still this number of changes requires also a higher effort for the tool development which also means more development time.

 

Until then we have to stick to the godd ol' stuff we're used to.

 

Kind regards

  Eilert

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Historian
Historian
11,085 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@eilert wrote:

 

You pointed out to have the Entity and Architectures in the same file. But why?

A very common alternative method is to have a separate file for each code segment (ent,arc,cfg,pkg).

Configurations select the architectures by their specific names, same could be done with file names.

So the entity for some function would always remain the same, and e.g. in some tcl script only the architecture names would be different according to the target technology.

 

Of course its a matter of personal taste which method is used by a designer (team) .


 

I didn't mean to imply that the architectures had to be in the same source as the entity (apologies if that's how it came across), but I find it convenient.

 

The reason I suggest putting all architectures in the same source is simple: I don't want source files in my tree which are not used. Invariably, someone else will need to look at the design and look at the sources and realize, "oh, mem_s3.vhdl isn't used ... grrr ... why is it even here?"

 

So certainly, the one source file which contains the entity declaration and the two architectures might be large. TANSTAAFL.

 

 

 


Many methods work and have their advantages and drawbacks.

Some people prefer having separate scripts for jumping between implementation and/or simulation flows.

Others have separate toplevel HDL files for that purpose.

In the end, if done properly, all methods should yield the same result.


 

Indeed. My script-fu is seriously lacking, and keeping track of which files are used for this but not that can be tiresome. But whatever works!

----------------------------Yes, I do this for a living.
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Visitor jonas812
Visitor
11,003 Views
Registered: ‎11-07-2010

Re: VHDL-2008 support in Vivado

> The "(others => '0')" statement isn't supported in this case. At least it's not supported for

> Spartan 3E according to the technical support. Why should it be device dependend if a

> VHDL statement is supported or not?

 

It is because old devices use by default the old parser. If you add the option -use_new_parser yes in the Other XST Command Line Options (set Property display level = Advanced to see it) of the Synthesize - XST process, it should fix the problem.

 

Jonas

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Observer daniel.kho
Observer
6,150 Views
Registered: ‎09-19-2012

Re: VHDL-2008 support in Vivado

Sorry for chiming in late.

Actually I like that my simulator doesn't give me any proper output when the sensitivity list isn't properly defined.

 

Not too sure about Vivado, but Quartus gives a warning when you're reading from a signal that isn't in the sensitivity list.

And yes, Quartus supports "process(all)".

 

regards,

daniel

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Xilinx Employee
Xilinx Employee
6,135 Views
Registered: ‎08-14-2012

Re: VHDL-2008 support in Vivado

Hello There,

VHDL-2008 is not supported in vivado 2012.2. but it suppose to support in future version
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Adventurer
Adventurer
6,076 Views
Registered: ‎12-09-2010

Re: VHDL-2008 support in Vivado

I will celebrate the day that Xilinx starts to support VHDL-2008 properly. But I won't buy any champagne yet because I fear that the champagne could be unenjoyable till then. ;-)
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Historian
Historian
6,071 Views
Registered: ‎02-25-2008

Re: VHDL-2008 support in Vivado


@stmartin81 wrote:
I will celebrate the day that Xilinx starts to support VHDL-2008 properly. But I won't buy any champagne yet because I fear that the champagne could be unenjoyable till then. ;-)

Ah, then switch to single-malt Scotch.

----------------------------Yes, I do this for a living.
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Scholar pedro_uno
Scholar
2,178 Views
Registered: ‎02-12-2013

Re: VHDL-2008 support in Vivado

According to UG901, Vivado 2017.2 supports all the most important features of VHDL-2008 for synthesis.
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DSP in hardware and software
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