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doppioandante
Newbie
Newbie
378 Views
Registered: ‎06-26-2018

VHDL 2008 unconstrained generic synthesis regression from 2019.1 to 2020.2

Hello, I have recently upgraded my Vivado installation to 2020.2

The full code is at https://github.com/doppioandante/tesi and is open source, and a zipped version of the vivado project files is attached to this post.

The code I wrote that was working fine on Vivado 2019.1 is now failing on Vivado 2020.2

 

package rom is
    generic (
        word_bits: positive;
        address_bits: positive;
        rom_filename: string
    );

    subtype word_type is std_logic_vector(word_bits-1 downto 0);

    impure function read_at(address: in integer range 0 to 2**address_bits-1) return word_type;
end package rom;

 

 

The former is a generic rom package with variable address and word bits which gets instantiated from the rom_filename file. Example of how I use it:

 

    package phase_rom is new work.rom
    generic map(
        word_bits => phase_bits,
        address_bits => 7,
        rom_filename => "note_phase_table.txt"
    );

    package waveform_rom is new work.rom
    generic map(
        word_bits => sample_bits,
        address_bits => waveform_address_bits,
        rom_filename => "waveform_rom.txt"
    );

 

 

This worked fine in vivado 2019.1, but is now giving me the following errors in 2020.2:

 

[Synth 8-6032] unexpected vhdl node type '"note_phase_table.txt"' ["/home/enrico/projects/tesi/vhdl/Vivado_tesi/tesi.srcs/sources_1/imports/vhdl/synth_engine.vhd":31]
[Synth 8-27] VHDL 2008 Generic Type not supported ["/home/enrico/projects/tesi/vhdl/Vivado_tesi/tesi.srcs/sources_1/imports/vhdl/synth_engine.vhd":31]
[Synth 8-318] illegal unconstrained array generic 'rom_filename' ["/home/enrico/projects/tesi/vhdl/Vivado_tesi/tesi.srcs/sources_1/imports/vhdl/rom_pkg.vhd":11]
[Synth 8-78] a value must be associated with generic word_bits ["/home/enrico/projects/tesi/vhdl/Vivado_tesi/tesi.srcs/sources_1/imports/vhdl/rom_pkg.vhd":9]
[Synth 8-285] failed synthesizing module 'synth_engine' ["/home/enrico/projects/tesi/vhdl/Vivado_tesi/tesi.srcs/sources_1/imports/vhdl/synth_engine.vhd":26]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

 

 

3 Replies
varunra
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎01-24-2017

Hi,

filed CR for this issue

Thanks

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doppioandante
Newbie
Newbie
189 Views
Registered: ‎06-26-2018

Hi, any update on this? I can also upload a Vivado 2019 project file (the one that work) if it can be useful.

0 Kudos
varunra
Xilinx Employee
Xilinx Employee
137 Views
Registered: ‎01-24-2017

Hi, 

The issue has been file the they are looking into it.

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