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[VHDL] BEL is not an attribute (in a package) [Vivado 2017.2.1]

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Voyager
Posts: 1,444
Registered: ‎06-24-2013

[VHDL] BEL is not an attribute (in a package) [Vivado 2017.2.1]

The following code ...

package pkg is
attribute DONT_TOUCH : string;
attribute BEL : string; end package; library IEEE; use IEEE.std_logic_1164.ALL; library unisim; use unisim.VCOMPONENTS.ALL; use work.pkg.ALL; entity test is port (Q : out std_logic); end entity; architecture RTL of test is attribute DONT_TOUCH of LUT_inst : label is "TRUE"; attribute BEL of LUT_inst : label is "A6LUT"; begin LUT_inst : LUT1 port map (I0 => '1', O => Q); end RTL;

... results in a surprising error when synthesized ...

ERROR: [Synth 8-1026] bel is not an attribute [/bel_bug/bel.vhd:22]

... note that commenting out the DONT_TOUCH attribute declaration results in a different error ...

ERROR: [Synth 8-1031] dont_touch is not declared [/bel_bug/bel.vhd:23]

... and adding the BEL attribute declaration right before the attribute is assigned makes it work as expected.

 

Please consider fixing in a future release.

 

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
Explorer
Posts: 167
Registered: ‎04-12-2017

Re: [VHDL] BEL is not an attribute (in a package) [Vivado 2017.2.1]

I am not sure about this, but, can you use in an entity, attributes that were defined in a package?

 

I thought attributes were local to a block (entity, package, etc.)

Avi Chami MSc
FPGA Site
Voyager
Posts: 1,444
Registered: ‎06-24-2013

Re: [VHDL] BEL is not an attribute (in a package) [Vivado 2017.2.1]

Hey @a_chami,

 

can you use in an entity, attributes that were defined in a package?

The standard is quite clear here (1076-1993) ...

Items declared immediately within a package declaration become visible by selection within a given design unit wherever the name of that package is visible in the given unit. Such items may also be made directly visible by an appropriate use clause (see 10.4).

 

Best,

Herbert

-------------- Yes, I do this for fun!
Xilinx Employee
Posts: 1,355
Registered: ‎02-16-2014

Re: [VHDL] BEL is not an attribute (in a package) [Vivado 2017.2.1]

[ Edited ]

Hi @hpoetzl

 

Filed CR#985174 for this issue.

 

 

Thanks,
Manusha

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