11-22-2011 05:06 PM
I am working on a tic-tac-toe design project.
The project mandates for when the game ends in a tie (draw) that we use the same two LEDs we would light for if the player won or the machine won. The player output green LED would light only if it won and the machine red LED would light only if it won. If there is a tie both the win player and machine LEDs should light.
The problem I see in my code is that the WDR LED stays "U" even after I reset the WDR signal = '0' in the reset sequence. The WDG signal gets set to '0 in the reset process without any issues but the WDR signal stays as undefined. [Where WDG = the win/draw output LED for the player and WDR = the win/draw LED for the machine].
Here are my concurrent statements that are placed withing the arhitecture but outside of any processes.
WDG <= sWDG or ((sG1 or sR1) and (sG2 or sR2) and (sG3 or sR3) and (sG4 or sR4) and (sG5 or sR5) and (sG6 or sR6) and (sG7 or sR7) and (sG8 or sR8) and (sG9 or sR9) and (not sWDG) and (not sWDR))
WDR <= sWR or ((sG1 or sR1) and (sG2 or sR2) and (sG3 or sR3) and (sG4 or sR4) and (sG5 or sR5) and (sG6 or sR6) and (sG7 or sR7) and (sG8 or sR8) and (sG9 or sR9) and (not sWDG) and (not sWDR))
sWDG = signal for when the player wins
sG1-sG9 = signals for the output LEDs that represent the squares on the tic tac toe board (each square can either be a green LED (meaning the player took that square) and red LED (meaning the machine took that square)
Any suggestions why the WDR signal stays "U" (undefined)? Thanks for everyones help!!
11-22-2011 06:15 PM - edited 11-22-2011 06:16 PM
One of the values on the RHS of your CSA must be "U". If existed multiple drivers, you would see an 'X' instead. Try commenting all but the first part of your CSA. Keep adding a little but more until the 'U' appears in your simulation.
11-25-2011 04:08 AM
I can't understand what it is wrong in the lines that you have wrote. I would need a watch of the environment.
Can you explain me how you generate sWDR signal?
11-25-2011 06:17 AM
Please check the RTL Schematic and Technology Viewer after synthesis. See if the synthesized logic makes sense.
11-27-2011 07:41 PM
You can also run simulation to trace why the signal in question is U.