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Explorer
Explorer
344 Views
Registered: ‎01-13-2018

VHDL Conversion help

I need to convert a Verilog statement into VHDL. I am not sure if I have done it in correct way. Here I am posting both for review. Please have a look at it and let me know if it correct or wrong. Thanks. 

Verilog: 

wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && 
             (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && 
             (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));

VHDL: 

  if ((wr_ptr_gray_reg(GC_ADDR_WIDTH) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH)) and 
             (wr_ptr_gray_reg(GC_ADDR_WIDTH-1) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-1)) and 
             (wr_ptr_gray_reg(GC_ADDR_WIDTH-2 downto 0)= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-2 downto 0))) then 
			 
			 full <= '1'; 
			 else 
			 full <= '0';
			 end if; 

 

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2 Replies
Explorer
Explorer
328 Views
Registered: ‎03-17-2011

Re: VHDL Conversion help

full <= '1' when  ((wr_ptr_gray_reg(GC_ADDR_WIDTH) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH)) and 
             (wr_ptr_gray_reg(GC_ADDR_WIDTH-1) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-1)) and 
             (wr_ptr_gray_reg(GC_ADDR_WIDTH-2 downto 0)= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-2 downto 0))) else '0';

Maybe this should work.

--Sebastien
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298 Views
Registered: ‎01-08-2012

Re: VHDL Conversion help

Verilog doesn't distinguish between boolean and logic types; VHDL does.  If you have declared full as a boolean signal, the code could look very similar to the Verilog original:

full <= ((wr_ptr_gray_reg(GC_ADDR_WIDTH) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH)) and 
         (wr_ptr_gray_reg(GC_ADDR_WIDTH-1) /= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-1)) and 
         (wr_ptr_gray_reg(GC_ADDR_WIDTH-2 downto 0)= rd_ptr_gray_sync2_reg(GC_ADDR_WIDTH-2 downto 0)));

If full is a variable (rather than a signal) the code would look the same but with <= replaced by :=

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