04-19-2021 05:52 AM - edited 04-19-2021 06:27 AM
Hope that you are staying healthy and at a safe place, despite the ongoing lockdown.
I have a problem with a component declaration.
In the simulation I am going to use one component two times.
PS I dont want to rewrite the component and create two input and two output signals.
I declare the component two times as :
U_FIR_1 : FIR -- inphase signal PORT MAP ( input => input_inphase, out => out_inphase ); U_FIR_2 : FIR-- quadrature PORT MAP ( input => input_quadrature, out => out_quadrature );
in the main process, I have to define the inputs of the `U_FIR_1` ( is `input_quadrature`) and `U_FIR_2 ` ( is `input_quadrature`) .
-- For U_FIR_1 input <= input_quadrature; ??? -- For U_FIR_2 input <= input_inphase; ???
Is it possible to declare the component (FIR) 2 times ( as I have described above)?
04-19-2021 06:06 AM
Do you mean something like this?
FirI_d1 : dec1_101t_16ch PORT Map( aresetn => FIR1_resetn, aclk => clk200, s_axis_data_tvalid => input_tvalid, s_axis_data_tready => input_tready, s_axis_data_tuser => input_tuser, s_axis_data_tdata => input_inphase, m_axis_data_tvalid => output_tvalid, m_axis_data_tuser => output_tuser, m_axis_data_tdata => output_inphase, event_s_data_chanid_incorrect => chanid_incorrect ); FirQ_d1 : dec1_101t_16ch PORT Map( aresetn => FIR1_resetn, aclk => clk200, s_axis_data_tvalid => input_tvalid, s_axis_data_tready => OPEN, s_axis_data_tuser => input_tuser, s_axis_data_tdata => input_quadrature, m_axis_data_tvalid => OPEN, m_axis_data_tuser => OPEN, m_axis_data_tdata => output_quadrature, event_s_data_chanid_incorrect => OPEN );
04-19-2021 07:25 AM
I don't understand your question. Are you asking how to define input_inphase and input_quadrature? What is the input to your top level process? Does the input to the top level process come in on the same clock that the filters are using? The filters are using a clock, right? Are input_inphase and input_quadrature signed, unsinged, std_logic_vectors or something else?
04-19-2021 07:34 AM
Are you mixing up instantiating and declaration ?
04-19-2021 10:47 PM - edited 04-19-2021 10:50 PM
FIR is a function ( another .vhd file), which I use two time. I apply it for a signal "input_inphase" and for a signal "input_quadrature".
I added two signal (new version):
signal fir_filter_input_inphase : std_logic_vector ( (bits-1) downto 0); signal fir_filter_input_quadrature : std_logic_vector ( (bits-1) downto 0);
and in the CLK process:
if (counter = 0) then fir_filter_input_quadrature <= input_quadrature; fir_filter_input_inphase <= input_inphase; -- input_quadrature<= input_quadrature; -- input_inphase<= input_inphase; else --if the counter is not equal tp 0 a 0 goes into the output, fir_filter_input_quadrature <= (others => '0'); ir_filter_input_inphase <= (others => '0');
My goal : add zero-valued samples between the samples and then filtere the signal ( I have two signal)
and I have changed
U_FIR_1 : FIR -- inphase signal PORT MAP ( input => fir_filter_input_inphase, out => out_inphase ); U_FIR_2 : FIR-- quadrature PORT MAP ( input => fir_filter_input_quadrature , out => out_quadrature );
04-20-2021 12:42 AM - edited 04-20-2021 12:49 AM
is FIR a function in another file, or is it another entity ?
Did you read that free download on VHDL ,
The problem Im seeing
is that you are trying to describe a technical question, using the correct language , but the wrong words,
so we are at best confused, at worst liable to offer you the wrong advise.
04-20-2021 01:08 AM
Your new version of code looks good.
You can run simulation to verify the function.
04-20-2021 04:50 AM
Thank you, I understand how I can fix it.
As you have already probably understand, I am using "counter" to add 0s into input signals.
counter:= counter + 1; --if the counter is 0 a data sample goes into the output, if (counter = 0) then fir_filter_input_quadrature <= input_quadrature; fir_filter_input_inphase <= input_inphase; else --if the counter is not equal tp 0 a 0 goes into the output, fir_filter_input_quadrature <= (others => '0'); fir_filter_input_inphase <= (others => '0'); end if; -- if(counter=0) then --if the counter is > 3 ( M = 4), if (counter > ( M - 1)) then counter:= 0; end if;
it is a part of the second file " IntFiR" ( the first one is FIR). IntFiR adds 0s between two adjacent elements of the input vectors and creates the new inputs for FIR file.
I am trying to merge two files in one and have only one FIR, which will add 0s and filters the signals. My idea is to use clk instead of counter. " the data is available only in each 4s clk..." smth like this.
Is it possible to implement in vhdl? if yes, could you provide me some example of such simulation?
04-20-2021 04:58 AM
@asai9493 What you are describing is an interpolating filter with two parallel paths. While writing your own is a good learning experience, the FIR Compiler Product Guide (PG149) describes exactly this. The FIR IP is resource efficient and in most cases, fairly easy to use. It is worth the time lo look into the FIR Compiler.
04-20-2021 06:59 AM - edited 04-20-2021 07:10 AM
so how are you defining counter, Std_logic_vector, integer, unsigned ?
the if counter = 0 line is implementing a wide gate , depending upon the counter width,
you would probably be better off decoding the counter max value, i.e. th eone beofre 0, and generating a logic '1', for one clock, which is registered to arrive at same time as counter = 0 would,
this would give you a nice compact, de glitched control signal for the wide input MUX you have created.
If you can convert the MUX to a synchronous MUX, i.e. with a clock also better,
it adds to the pipeline delay , but will make routing and timing much easier,
You already have a huge delay through thr FIR, so I'd say that a few more clocks will not matter to your design.
I'm also guessing that your FIR is not a VHDL function , but a VHDL entity which your instantiating in a higher level architecture,
As such , FIR can be instantiated any number of times in the higher architecture.
Its good to get the correct wording form the beginning, it helps every one.
Note, if you instantiate two FIRs, then you will double the amount of logic in the FPGA.
this may or may not be what you intend.
You can think of instantiation like putting chips into sockets,
Once ou have defined the chip, you can put many of the same type into a board.
04-20-2021 07:57 AM
>Did you read that free download on VHDL
You get what you pay for. The book by a "he/him/his" is as silly as thinking it necessary to tell me he is a he. Please look for a better book to recommend.
04-20-2021 08:14 AM - edited 04-20-2021 08:55 AM
>My goal : add zero-valued samples between the samples and then filtere the signal - @asai9493
Just upload your code. It's probably not as valuable as you might think, has been done better by a lot of engineers, and it will allow us to help you better.
With the snippets you posted, it sounds like you're trying to do an interpolating upsampling filter and are on the right track. The only thing I would do differently is to generate a CE based on the counter. Xilinx calls it a CE for "clock enable" but it is really a "data enable"--sometimes they call it "chip enable".
In any event, something like this (not syntax checked) might be useful:
constant kMAX_CNT : integer := 4; -- set to whatever the interpolation rate is signal counter : integer range 0 to kMAX_CNT - 1 := 0; begin -- architecture PROC_GEN_CE : process (iClk) begin if (rising_edge(iClk)) then if((kMAX_CNT -1) = counter) then counter <= 0; myce <= '1'; else counter <= counter + 1; myce <= '0'; end if; end process PROC_GEN_CE; PROC_ZERO_STUFF : process (iClk) begin if (rising_edge(iClk)) then if('1' = myce) then fir_filter_quadrature <= input_quadrature; -- assumes stable, may need input valid and pipelining depending on your actual design fir_filter_inphase <= input_inphase; else -- the CE in this case muxes between valid data and constant literal 0s, so it will probably infer a synchronous reset fir_filter_quadrature <= (others => '0'); fir_filter_inphase <= (others => '0'); end if; end if; end process PROC_ZERO_STUFF;
I am assuming you're just trying to learn. If this were a real problem, I agree with @bruce_karaffa to go first to the IP catalog, and add you should also take a look at UG901 in docNav as it has FIR code you can compare yours against.
04-20-2021 11:45 PM
> so how are you defining counter, Std_logic_vector, integer, unsigned ?
I defined it as
variable counter : integer range 0 to (M - 1) := 0;
I cant use FIR IP, my task is implementation of FIR interpolation filter. "FIR" is my implementation of the filter with adders, multipliers und shift datas.
04-20-2021 11:54 PM - edited 04-21-2021 12:02 AM
04-21-2021 12:00 AM - edited 04-21-2021 12:11 AM
signal counter : integer range 0 to kMAX_CNT - 1 := 0;
Should it be after the following line ?
architecture Behavioral of FIR is
2) myce, should be defined in "entity" as
myce : out std_logic;
04-21-2021 12:04 AM
>I am assuming you're just trying to learn. If this were a real problem, I agree with @bruce_karaffa to go first to the IP catalog, and add you should also take a look at UG901 in docNav as it has FIR code you can compare yours against.
I have seen FIR in IP catalog, but I cant use it. I have to implement it without IP catalog. I can use IP catalog for math functions