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Voyager
Voyager
340 Views
Registered: ‎06-20-2017

VHDL Procedure not synthesized correctly

rtl1 and rtl3 both synthesize correctly.

rtl2, synthesizes, but ties the CE to a '1' post synthesis.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity my is
  port ( 
    iCLK : IN  std_logic;
    iD   : IN  std_logic;
    iEn  : IN  std_logic;
    oY   : OUT std_logic
  );
end entity my;

architecture rtl1 of my is
  signal y : std_logic := '0';
begin

  MY_PROCESS : process (iCLK)
  begin
    if (rising_edge(iCLK)) then
      if (iEn = '1') then
        y <= iD;  
      end if;
    end if;
  end process MY_PROCESS;

  oY <= y;

end architecture rtl1;

architecture rtl2 of my is

  procedure dff_en(
    signal clk          : IN  std_logic;
    signal input_data   : IN  std_logic;
    signal input_enable : IN  std_logic;
           output_data  : OUT std_logic
    ) is
  begin -- procedure
    if(rising_edge(clk))then
      if(input_enable = '1') then
        output_data := input_data;
      end if;
    end if;
  end procedure dff_en;
  shared variable my_var : std_logic; -- stupid, I know, but legal syntactically per synthesis parser, and synthesis pattern matches it to a DFF.
begin

  dff_en(
    clk          => iCLK,
    input_data   => iD,
    input_enable => iEn,
    output_data  => my_var
  );
  oY <= my_var;

end architecture rtl2;

architecture rtl3 of my is

  procedure dff_en(
    signal clk          : IN  std_logic;
    signal input_data   : IN  std_logic;
    signal input_enable : IN  std_logic;
    signal output_data  : OUT std_logic
    ) is
  begin -- procedure
    if(rising_edge(clk))then
      if(input_enable = '1') then
        output_data <= input_data;
      end if;
    end if;
  end procedure dff_en;
begin

  dff_en(
    clk          => iCLK,
    input_data   => iD,
    input_enable => iEn,
    output_data  => oY
  );

end architecture rtl3;
Adaptable Processing coming to an IP address near you.
wrong.PNG
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5 Replies
Scholar richardhead
Scholar
325 Views
Registered: ‎08-01-2012

Re: VHDL Procedure not synthesized correctly

I'm actually surprised it works at all.
The problem here is the use of a shared variable. Shared variables have no timing info. So if you simulated rtl2, oY would be locked at 'U' forever because it has no 'events to trigger an update on oY. If anything, the error is that it created any logic at all. This is why shared variables like this should be avoided.

So all bets are off.
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Voyager
Voyager
301 Views
Registered: ‎06-20-2017

Re: VHDL Procedure not synthesized correctly

Well, it synthesizes.  I wonder if Xilinx will notice this report now that it has turned into a discussion? 

 

(BTW, this was an academic exercise, best to override default class of procedure output to signal.)

Adaptable Processing coming to an IP address near you.
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Mentor hgleamon1
Mentor
278 Views
Registered: ‎11-14-2011

Re: VHDL Procedure not synthesized correctly

What does the synthesis report state about rtl2?

Secondly, academic exercise aside, I cannot fathom why you would want to use a procedure to replace a process .. ? 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Voyager
Voyager
195 Views
Registered: ‎06-20-2017

Re: VHDL Procedure not synthesized correctly

>Secondly, academic exercise aside, I cannot fathom why you would want to use a procedure to replace a process .. ? 

I agree.

Take it up with IEEE or synthesizer vendors.

Incidentally, participants here need to understand that this is a support forum, and not reddit.

Because when you answer posts not yet addressed by Xilinx, it seems to discourage Xilinx support staff from responding. 

Adaptable Processing coming to an IP address near you.
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Mentor hgleamon1
Mentor
175 Views
Registered: ‎11-14-2011

Re: VHDL Procedure not synthesized correctly

"Xilinx provides these discussion boards as a service to its users and customers, to help them exchange ideas, tips, information, and techniques related to Xilinx products"

I disagree that community responses "discourages" Xilinx from responding. It is a community. Participants are actively encouraged to provide "ideas, tips, information".

You have asked an interesting question that could affect a number of other users, including Xilinx themselves. I asked about the synthesis report for rtl2 so that we, as a community, can delve deeper into why it doesn't do what you expect.

If you posted the same question across any other internet VHDL or FPGA forum I would expect a similar response to "why are you doing this?".

----------
"That which we must learn to do, we learn by doing." - Aristotle
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