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Adventurer
Adventurer
567 Views
Registered: ‎07-24-2016

[VHDL] Record of Record

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Hi,

Is there any way to create a record of another record in VHDL?

Suppose that I have a record of 4 registers:

    type registers_record is record
        register_0  : std_logic_vector(31 downto 0);
        register_1  : std_logic_vector(31 downto 0);
        register_2  : std_logic_vector(31 downto 0);
        register_3  : std_logic_vector(31 downto 0);
    end record;

And register_0 has some bitfields, e.g. bit-31 is pll_lock, [30:21] is cnt_limit and [20:0] is latency,

    type register_0 is record
        pll_lock    : std_logic;
        cnt_limit   : std_logic_vector(9 downto 0);
        latency     : std_logic_vector(20 downto 0);
    end record;

And I would like to do this in my actual RTL:

signal regs_record : registers_record;
signal mmcm_lock : std_logic := '0'; -- connected to an MMCM pin regs_record.register_0.pll_lock <= mmcm_lock;

Which of course, gives me an error.  What am I doing wrong?

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1 Solution

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Scholar richardhead
Scholar
514 Views
Registered: ‎08-01-2012

Re: [VHDL] Record of Record

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A record is just a composite type - each field can be any type. So you can nest records inside records.

So you can decalre like this:

type register_0_t is record
        pll_lock    : std_logic;
        cnt_limit   : std_logic_vector(9 downto 0);
        latency     : std_logic_vector(20 downto 0);
end record;

type register_record_t is record
  register_0  : register_0_t;
  register_1 : register_1_t;
end record;

regs.register_0.pll_lock <= mmcm_locked;
2 Replies
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Scholar richardhead
Scholar
515 Views
Registered: ‎08-01-2012

Re: [VHDL] Record of Record

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A record is just a composite type - each field can be any type. So you can nest records inside records.

So you can decalre like this:

type register_0_t is record
        pll_lock    : std_logic;
        cnt_limit   : std_logic_vector(9 downto 0);
        latency     : std_logic_vector(20 downto 0);
end record;

type register_record_t is record
  register_0  : register_0_t;
  register_1 : register_1_t;
end record;

regs.register_0.pll_lock <= mmcm_locked;
Xilinx Employee
Xilinx Employee
510 Views
Registered: ‎02-16-2014

Re: [VHDL] Record of Record

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Hi @cbakal

 

Define record type for the elements of register_0 first and then use that as element type in your registers_record.

for example,

 

type rec1 is record
pll_lock : std_logic;
cnt_limit : std_logic_vector(9 downto 0);
latency : std_logic_vector(20 downto 0);
end record;

type registers_record is record
register_0 : rec1;
register_1 : rec1;
register_2 : rec1;
register_3 : rec1;
end record;