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Voyager
Voyager
1,873 Views
Registered: ‎06-24-2013

VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

The following VHDL code ...

library IEEE;
use IEEE.std_logic_1164.ALL; library unisim; use unisim.VCOMPONENTS.ALL; entity test is port (Q : out std_logic); end entity; architecture RTL of test is signal I : std_logic_vector(2 downto 0) := (others => '1'); begin LUT_inst : LUT3 port map ( I0 => I(0), I1 => I(1), I2 => I(2), O => Q); I(0) <= '1'; -- remove me end RTL;

... produces a rather unexpected result ...

def_gnd.png ... but when you remove the assignment for I(0), the default works as expected ...

def_vcc.png

Please consider fixing this ...

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
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8 Replies
Xilinx Employee
Xilinx Employee
1,855 Views
Registered: ‎02-16-2014

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hi @hpoetzl

 

Is this in 2017.2.1?

I tried in 2017.2.1 and with both versions of RTL code, I could see I(0) is connected to const1.

 

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Xilinx Employee
Xilinx Employee
1,839 Views
Registered: ‎02-14-2014

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hi @hpoetzl,

 

Would be helpful if you can share the output of command version to know SW Build number. 

Regards,
Ashish
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Moderator
Moderator
1,838 Views
Registered: ‎11-09-2015

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hi @hpoetzl,

 

I have tried in 2017.2.1 and I cannot reproduce your issue:

LUT.PNG

 

Could you try to initialize the truth table of your LUT see if you have the same behavior?

 

Also check the truth table of your LUT in both case. It could have change (thus this would not be a bug but a different synthesis result (the behaviour would be the same))

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Voyager
Voyager
1,814 Views
Registered: ‎06-24-2013

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

 

@pulim: Is this in 2017.2.1?

Yes, as the subject says, Vivado 2017.2.1.

 

with both versions of RTL code, I could see I(0) is connected to const1.

Yes, that is the expected part, the unexpected is that I(1) and I(2) get tied to ground.

 

@ashishd: ... output of command version to know SW Build number?

 Here you go ...

****** Vivado v2017.2.1 (64-bit)
  **** SW Build 1957588 on Wed Aug  9 16:32:10 MDT 2017
  **** IP Build 1948039 on Wed Aug  9 18:19:28 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

 

@florentw: ... check the truth table of your LUT in both cases ...

I initialized and verified the truth table in both cases and it is unchanged and identical.

 

I've wrapped everything up in an example with logs from both elaborations.

There are logs with and without the assignment and the relevant difference is ...

WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I1 to constant 0 [/init_bug/init.vhd:28]
WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I2 to constant 0 [/init_bug/init.vhd:28]

 

Thanks again,

Herbert

-------------- Yes, I do this for fun!
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Moderator
Moderator
1,787 Views
Registered: ‎11-09-2015

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hi @hpoetzl,

 

I am able to reproduce your issue. This is not really an issue with synthesis because the schematic you are opening is on the elaborated design...

 

If you remove the -rtl option you will synthesize the design and have no issue in the synthesized design.

 

However I acknowledge the issue on the elaborated design and I will report it to development (however because it does not affects the synthesis or implementation, not sure if it will get high priority).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Voyager
Voyager
1,776 Views
Registered: ‎06-24-2013

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hey @florentw,

 

I am able to reproduce your issue.

Excellent!

 

However I acknowledge the issue on the elaborated design and I will report it to development.

Thanks, appreciated!

 

however because it does not affects the synthesis or implementation, not sure if it will get high priority.

I hope it will, as elaboration can be a quite useful tool to verify that the design is what you actually want, but if the result does not match up with synthesis, it becomes rather useless.

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Moderator
Moderator
1,770 Views
Registered: ‎11-09-2015

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Hi @hpoetzl,

 

I confirm that I have reported this issue to development for a fix in a future release.

 

If everything is clear for you, could you mark the issue a "solved"? (Not sure if solved is the correct word, but at least meaning that everything is clear ;) )

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Voyager
Voyager
1,766 Views
Registered: ‎06-24-2013

Re: VHDL Synthesis Bug with Defaults [Vivado 2017.2.1]

Everything clear for me.

 

I'll mark the thread as 'solved' once the issue has been resolved.

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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