09-11-2017 12:41 AM
The following VHDL code ...
use IEEE.std_logic_1164.ALL; library unisim; use unisim.VCOMPONENTS.ALL; entity test is port (Q : out std_logic); end entity; architecture RTL of test is signal I : std_logic_vector(2 downto 0) := (others => '1'); begin LUT_inst : LUT3 port map ( I0 => I(0), I1 => I(1), I2 => I(2), O => Q); I(0) <= '1'; -- remove me end RTL;
... produces a rather unexpected result ...
... but when you remove the assignment for I(0), the default works as expected ...
Please consider fixing this ...
Thanks in advance,
09-11-2017 02:05 AM
09-11-2017 02:46 AM
Would be helpful if you can share the output of command version to know SW Build number.
09-11-2017 02:48 AM
I have tried in 2017.2.1 and I cannot reproduce your issue:
Could you try to initialize the truth table of your LUT see if you have the same behavior?
Also check the truth table of your LUT in both case. It could have change (thus this would not be a bug but a different synthesis result (the behaviour would be the same))
09-11-2017 09:56 AM
@pulim: Is this in 2017.2.1?
Yes, as the subject says, Vivado 2017.2.1.
with both versions of RTL code, I could see I(0) is connected to const1.
Yes, that is the expected part, the unexpected is that I(1) and I(2) get tied to ground.
@ashishd: ... output of command version to know SW Build number?
Here you go ...
****** Vivado v2017.2.1 (64-bit) **** SW Build 1957588 on Wed Aug 9 16:32:10 MDT 2017 **** IP Build 1948039 on Wed Aug 9 18:19:28 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
@florentw: ... check the truth table of your LUT in both cases ...
I initialized and verified the truth table in both cases and it is unchanged and identical.
I've wrapped everything up in an example with logs from both elaborations.
WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I1 to constant 0 [/init_bug/init.vhd:28] WARNING: [Synth 8-3295] tying undriven pin LUT_inst:I2 to constant 0 [/init_bug/init.vhd:28]
09-12-2017 01:50 AM
I am able to reproduce your issue. This is not really an issue with synthesis because the schematic you are opening is on the elaborated design...
If you remove the -rtl option you will synthesize the design and have no issue in the synthesized design.
However I acknowledge the issue on the elaborated design and I will report it to development (however because it does not affects the synthesis or implementation, not sure if it will get high priority).
09-12-2017 07:29 AM
I am able to reproduce your issue.
However I acknowledge the issue on the elaborated design and I will report it to development.
however because it does not affects the synthesis or implementation, not sure if it will get high priority.
I hope it will, as elaboration can be a quite useful tool to verify that the design is what you actually want, but if the result does not match up with synthesis, it becomes rather useless.
09-12-2017 08:05 AM
I confirm that I have reported this issue to development for a fix in a future release.
If everything is clear for you, could you mark the issue a "solved"? (Not sure if solved is the correct word, but at least meaning that everything is clear ;) )
09-12-2017 08:40 AM
Everything clear for me.
I'll mark the thread as 'solved' once the issue has been resolved.