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Explorer
Explorer
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Registered: ‎09-08-2009

VHDL case statement without priority

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How I can "avoid priority processing"  in a case statement using Vivado 2018.3, VHDL language

in other words I am looking for the VHDL equivalent of  Verilog parallel_case,

 

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Guide
Guide
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Registered: ‎01-23-2009

Because the syntax and rules of the VHDL case statement are more limited than the one in Verilog, all VHDL case statements are parallel. In VHDL the case condition must be a simple signal with a defined set of values, and all the case conditions must be simple values. Furthermore case conditions for all values of the signal me specified, either in explicitly, in a range, or via the "default" clause, and values cannot be part of more than one case item. Because of this limited syntax, the case statement in VHDL is always parallel (and full).

In Verilog, pretty much none of these rules apply. Both the case condition and the case items can both be arbitrarily complex expressions with no restriction on what they evaluate to, nor any restriction on being complete (covering all values) or mutually exclusive. As a result, this opens the door for cases to be "full" or not "full", and "parallel" or not "parallel". While this is not a problem for the language, these different combinations synthesize to different hardware, with a non-parallel case generally being much slower and bigger than a parallel case. So most synthesis tools started supporting pragmas to tell the synthesis tool which one it was (when it wasn't clear from the coding), which eventually became standard, and then later introduced the SystemVerilog "unique case" and "priority case" statements.

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Guide
Guide
234 Views
Registered: ‎01-23-2009

Because the syntax and rules of the VHDL case statement are more limited than the one in Verilog, all VHDL case statements are parallel. In VHDL the case condition must be a simple signal with a defined set of values, and all the case conditions must be simple values. Furthermore case conditions for all values of the signal me specified, either in explicitly, in a range, or via the "default" clause, and values cannot be part of more than one case item. Because of this limited syntax, the case statement in VHDL is always parallel (and full).

In Verilog, pretty much none of these rules apply. Both the case condition and the case items can both be arbitrarily complex expressions with no restriction on what they evaluate to, nor any restriction on being complete (covering all values) or mutually exclusive. As a result, this opens the door for cases to be "full" or not "full", and "parallel" or not "parallel". While this is not a problem for the language, these different combinations synthesize to different hardware, with a non-parallel case generally being much slower and bigger than a parallel case. So most synthesis tools started supporting pragmas to tell the synthesis tool which one it was (when it wasn't clear from the coding), which eventually became standard, and then later introduced the SystemVerilog "unique case" and "priority case" statements.

Avrum

View solution in original post