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Visitor car.oro
Visitor
1,738 Views
Registered: ‎12-22-2018

VHDL help with latch

Someone can help me to avoid this warning? The code is:

signal 'signal': STD_LOGIC := '0';

name_process: process (A, B)
 
begin
if ( A = '1' and B = '1' ) then
       signal <= not signal;
else   
       signal <= signal;       
end if;
end process;
 
 
in which 'A' and 'B' are input  STD_LOGIC and 'signal' is a signal STD_LOGIC.
the warning is "WARNING:Xst:737 - Found 1-bit latch for signal <signal>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems."
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30 Replies
Explorer
Explorer
1,732 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

Hi @car.oro

this statement: signal <= not signal; is wrong in a asynchronous process.

If you want to keep this, you need to add a clock and make if a synchronous process.

 

--Sebastien
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Visitor car.oro
Visitor
1,723 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

I also tried it, but my signal have to change only when A and B are 1, not also when my clk is on rising edge

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Explorer
Explorer
1,711 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

Well the flip flop created within the synchronous process is a memory of one bit to store the signal value.

If you can't use it, you need to accept the latch but it's not recommanded.

 

--Sebastien
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Visitor car.oro
Visitor
1,709 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

How can I use it? I have to avoid the latch

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Explorer
Explorer
1,702 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

I'd code like this:

process(clk)
begin
   if rising_edge(clk) then
        if ( A = '1' and B = '1' ) then
            signal <= not signal;
        end if;
    end if;
end process;

Be advised that signal will only be updated on rising edge of the clock.

--Sebastien
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Scholar drjohnsmith
Scholar
1,700 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

do you follow why your getting the latch ?

as a suggestion, can you use the two signals as enables, to a clocked process ?

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor car.oro
Visitor
1,699 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

in this case, my signal changed every time that I'm on rising edge.. but I need that it changed only when A and B are 1 (so, for example, if I have A=1 and B=1 for more clocks, it have to change only the first time)

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Visitor car.oro
Visitor
1,694 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

yes I understand why I get the latch, but I don't understand how to resolve

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Explorer
Explorer
1,690 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

No, your signal will only be inverted (toggle) whenever the A=1 & B =1 condition is true at each rising edge of the clock.

Otherwise, signal is memorized (it will stay still).

--Sebastien
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Scholar drjohnsmith
Scholar
1,685 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

What Im hearing is you want to detect when A and B go to '1' , and then toggle the output.
what happens is A goes to 1 ahead of B, do you want to toggle once when B get to '1' , or not toggle because both A and B did not go to 1 together.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor car.oro
Visitor
1,680 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

yes, but I need that if A and B are 1 for more clocks, the signal will be inverted only at the first rising edge, not for every rising edge.
For example, if in the test bench I had:

A<='1';
B<='0';
wait for 10 ns;

A<='1';
B<='1';
wait for 10 ns;

A<='1';
B<='1';
wait for 10 ns;

A<='0';
B<='1';
wait for 10 ns;


A<='1';
B<='1';
wait for 10 ns;


if my signal is 0 when A=1 & B=0, it became 1 when A=1 & B=1, but after 10ns, when I have again A=1 & B=1, it will still be 1. Then, A became 0 and my signal will still be 1. When I have again A=1 & B=1, now it will inverted to 0

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Explorer
Explorer
1,663 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

I guess even your asynchronous process was not behaving like that.

--Sebastien
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Visitor car.oro
Visitor
1,651 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

my asynchronous process behaving like I told in my last reply because in the sensitivity list there are only A and B, so it toggle only when the input changed

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Explorer
Explorer
1,644 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

It would not work the same way on the FPGA. signal is required in your sensitivity list. You should have also a warning related to this in synthesis.

You need to use a synchronous process and consider some kind of "lock" to prevent your signal from toggling at each clock cycle when your condition is met. the lock could be released when the condition is false.

--Sebastien
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Explorer
Explorer
1,640 Views
Registered: ‎03-17-2011

Re: VHDL help with latch


I have not simulated. but, it could be somthing like this.


process(clk, rstb)
begin
   if (rstb = '0') then
        signal <= '0';
        lock <= '0';
   elsif rising_edge(clk) then
        if ( A = '1' and B = '1'  and lock = '0') then
            signal <= not signal;
            lock <= '1';
        else
            lock <= '0';
        end if;
    end if;
end process;

--Sebastien
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Visitor car.oro
Visitor
1,632 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

rstb is a reset?
anyway, I already tried something like this, but it doesn't work. It changed two times and then it became stable, maybe because the lock signal changed after 1 time of clock and not immediatly, but if I use a variable it became 0 every time I begin the process.

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Explorer
Explorer
1,601 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

Yes it's a reset.

I suggest you review your testbench or put it on the next post. Is your clock a 10ns period?

--Sebastien
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Visitor car.oro
Visitor
1,526 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

There are my stimulus ( the vector "concorrente" is "A" and "B"):

-- insert stimulus here
rst<='1';
wait for clk_period;
rst<='0';
wait for clk_period;
concorrente <= "01";
wait for clk_period;
concorrente <= "00";
wait for clk_period;
concorrente <= "10";
wait for clk_period;
concorrente <= "00";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "00";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "00";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "01";
wait for clk_period;
concorrente <= "10";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "00";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "11";
wait for clk_period;
concorrente <= "01";
wait for clk_period;
wait;
end process;

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Explorer
Explorer
1,456 Views
Registered: ‎03-17-2011

Re: VHDL help with latch

If you're using my process, the reset is active low. So your stimuli are holding the flip flop in reset state.

Try this:

-- insert stimulus here
wait for clk_period;

rst<='0';
wait for clk_period;
rst<='1';

 

--Sebastien
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Visitor car.oro
Visitor
1,454 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

Yes I know that your reset is active when is low, infact when I used your code I write the inverted if condition. (if reset=1 then ). I'm sorry that I haven't specified before

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Scholar drjohnsmith
Scholar
1,428 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

WHere have you gotten to on this ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
1,409 Views
Registered: ‎03-15-2012

Re: VHDL help with latch

I think what you need is a simple rising_edge detection on a&b? Like

signal a_and_b_dly: std_logic;
... process begin wait until rising_edge(clk); a_and_b_dly <= a and b; if a_and_b_dly = '0' and (a and b) = '1' then signal <= not signal; end if; end process;

As already told, the original sensitivity list is incomplete. If this would be complete, the simulator would tell you, that signal would never stabilize when a and b are '1'. This would lead to a combinational loop, and in hw maybe an oszillator.

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Visitor car.oro
Visitor
1,380 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

it have the same problem of before: if I have more than 2 A=1 and B=1 consecutive, my signal behaves like: 1->0->1->1->1->....->1 when I need something like this: 1->0->0->...->0 (in case of more A=1 and B=1 consecutive)

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Scholar drjohnsmith
Scholar
1,351 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

I for one could do with a diagram from you, showing the A and B inputs and what you want the outputs to do . In particular what do you want the output to do when A and B change together, and the case where A changes ahead of B ( or vice versa ) . Some idea as to the speed / frequency of A / B changing would be of use also.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor car.oro
Visitor
1,342 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

I want that at every A=1 and B=1 NOT consecutive, my signal changed. But, if A=1 and B=1 are consecutive for more clocks, my signal toggled only one time. My project is a buzzer and A and B are the players. If the players pushed the buzzers together, the turn becomes of one of the two. If later will be another pushed together, the turn becomes of the one that haven't speak at the first together's pushed.

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Scholar drjohnsmith
Scholar
1,334 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

 

A picture of the timing diagram would be a great way to illustrate this question. 

There are two ways to approach this, asynchronous, or synchronous,

Your input signals are buttons , which are relatively slow compared to even the slowest clock.

   as such I'd be looking at a synchronous design.

This sounds like a fun high school project ?

Problems to solve.

a) the buttons are going to bounce, so first thing is to interface these and de bounce,  google de bounce. 

    This will involve sampling the A and B inputs with the clock .  

b)   Now you have clock synchronises signals, then you can use the synchronous process example. 

I'd suggest turning the A and B onto one clock pulses,   then use a state machine type of approach , but there are many ways of cracking this nut.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor car.oro
Visitor
1,328 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

can you tell me some examples of codes? thanks 

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Scholar drjohnsmith
Scholar
1,318 Views
Registered: ‎07-09-2009

Re: VHDL help with latch

many examples of those words on the web,
eg.
http://vhdlguru.blogspot.com/2017/09/pushbutton-debounce-circuit-in-vhdl.html

http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/essential_vhdl_pdfs/essential_vhdl107-127.pdf
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor car.oro
Visitor
1,279 Views
Registered: ‎12-22-2018

Re: VHDL help with latch

I've looked, but I don't think it's what I need..

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