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Explorer
Explorer
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Registered: ‎03-17-2011

Re: VHDL help with latch

Hi @car.oro,

Juste a quick follow up here. I believe you've had all the best solutions proposed based on what you told us.

Were you able to solve your issue?

I've seen two ideas for you:

1. my process with the lock

2. using a rising edge detection when your condition comes true.

both should work.

regards,

--Sebastien
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