VHDL: to and downto difference in for loop

[fpgalearner]

Hi,

in VHDL what is difference between:

FOR i IN 31 DOWNTO 0 LOOP

and

FOR i IN 0 TO 31 LOOP

in for loop.

Regards

P.S. in std_logic_vector I know one is little endian and other is big endian.

[sebo · Accepted solution]

@fpgalearner

FOR i IN 31 DOWNTO 0 LOOP

In your loop code, the index 'i' will vary from 31 down to 0.

FOR i IN 0 TO 31 LOOP

In your loop code, the index 'i' will vary from 0 up to 31.

[rshekhaw]

Hi @fpgalearner,

Please check this link, might be helpful:

https://stackoverflow.com/questions/7642000/downto-vs-to-in-vhdl

Thanks,

Raj.