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Explorer
Explorer
984 Views
Registered: ‎04-11-2016

VHDL: to and downto difference in for loop

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Hi,

in VHDL what is difference between:

FOR i IN 31 DOWNTO 0 LOOP

and

FOR i IN 0 TO 31 LOOP

in for loop.

Regards

P.S. in std_logic_vector I know one is little endian and other is big endian.

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1 Solution

Accepted Solutions
Explorer
Explorer
967 Views
Registered: ‎03-17-2011

Re: VHDL: to and downto difference in for loop

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@fpgalearner

FOR i IN 31 DOWNTO 0 LOOP

In your loop code, the index 'i' will vary from 31 down to 0.

FOR i IN 0 TO 31 LOOP

In your loop code, the index 'i' will vary from 0 up to 31.

 

--Sebastien
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2 Replies
Explorer
Explorer
968 Views
Registered: ‎03-17-2011

Re: VHDL: to and downto difference in for loop

Jump to solution

@fpgalearner

FOR i IN 31 DOWNTO 0 LOOP

In your loop code, the index 'i' will vary from 31 down to 0.

FOR i IN 0 TO 31 LOOP

In your loop code, the index 'i' will vary from 0 up to 31.

 

--Sebastien
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Xilinx Employee
Xilinx Employee
954 Views
Registered: ‎05-22-2018

Re: VHDL: to and downto difference in for loop

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Hi @fpgalearner,

Please check this link, might be helpful:

https://stackoverflow.com/questions/7642000/downto-vs-to-in-vhdl

Thanks,

Raj.

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