09-29-2020 02:44 AM - edited 09-29-2020 02:44 AM
I wanted to try out the unconstrained std_logic_vector arrays as stated in UG901 - VHDL2008 features:
Usually I was able to use (few) VHDL 2008 features inside a block diagram, when I had a top-level block in standard VHDL (before 2008). However, when having the above code inside a package, Vivado fails to synthesize and states:
Subtype of array must be constrained. Use VHDL 2008 instead [.../lib/pkg/src/ro_pkg/ro_misc.vhd:16]
The package itself and all files including the package are opened in VHDL2008 mode, except a top-level wrapper to get it compatible to Block Diagram.
I use Vivado 2019.1.
Is there any way to include the unconstrained array construct somewhere inside the block diagram?
09-29-2020 03:41 AM
If the top level connects to components that have 2008 ports, you need to also compile that file as vhdl 2008 (otherwise you can get cryptic errors)
The block diagram editor is fixed at using VHDL 1993 and I doubt it will change soon.
Any reason for having to use a block diagram? I highly recommend using HDL only if you're using VHDL 2008.
09-29-2020 04:09 AM
Top top level entity is VHDL 93 (or so) only. So I'm using only standard types as std_logic_vectors and std_logics. The top level instantiates a VHDL2008 entitiy but again with only standardized ports. Inside the 08 entity I load the package and instantiate other entities with VHDL08.
This method allows me, to use VHDL08 features like if - else generics inside my hdl code, without Vivado complaining. However, when using the unconstrained vector, Vivado tells me that I should use VHDL2008.
> Any reason for having to use a block diagram? I highly recommend using HDL only if you're using VHDL 2008.
It's more for convenience, I mean it's good for an overview, despite some Vivado limitations.