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Scholar
Scholar
342 Views
Registered: ‎08-01-2012

[VHDL2019 Feature Request] Allow Partially Connected Vectors in portmaps

Previously, output ports in port maps needed to be wholly connected or left open. In VHDL 2019, this is no longer a requirement. Please implement this feature.

greatness : entity some_lib.some_ent
port map (
  some_output(7 downto 4) => some_4bit_signal,
  some_output(3 downto 0) => open
);
1 Reply
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Participant
Participant
260 Views
Registered: ‎03-21-2011

Until then....

some_output(3 downto 0) => dummy_signal_that_goes_nowhere_because_vivado_is_stupid

 

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